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PR9346: Prevent SimplifyDemandedBits from incorrectly introducing

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INT_MIN % -1.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
2011-03-09 01:28:35 +00:00
parent d7f3e7d046
commit c6b018b737
2 changed files with 16 additions and 0 deletions
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4
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -684,6 +684,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
break;
case Instruction::SRem:
if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
// X % -1 demands all the bits because we don't want to introduce
// INT_MIN % -1 (== undef) by accident.
if (Rem->isAllOnesValue())
break;
APInt RA = Rem->getValue().abs();
if (RA.isPowerOf2()) {
if (DemandedMask.ult(RA)) // srem won't affect demanded bits