mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
More DebugLoc propagation. This should be everything
except LegalizeOp itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63560 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
d64e0eb094
commit
c6be110f91
@ -231,7 +231,7 @@ private:
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SDValue BasePtr, const Value *SV,
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int SVOffset, unsigned Alignment,
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bool isVolatile, unsigned LdWidth,
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MVT ResType);
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MVT ResType, DebugLoc dl);
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/// StoreWidenVectorOp - Stores a widen vector into non widen memory
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/// location. It takes
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@ -257,7 +257,7 @@ private:
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SDValue BasePtr, const Value *SV,
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int SVOffset, unsigned Alignment,
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bool isVolatile, SDValue ValOp,
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unsigned StWidth);
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unsigned StWidth, DebugLoc dl);
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/// isShuffleLegal - Return non-null if a vector shuffle is legal with the
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/// specified mask and type. Targets can specify exactly which masks they
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@ -7481,8 +7481,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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#endif
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assert(0 && "Unhandled operation in SplitVectorOp!");
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case ISD::UNDEF:
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Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
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Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
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Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo);
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Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi);
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break;
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case ISD::BUILD_PAIR:
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Lo = Node->getOperand(0);
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@ -7494,10 +7494,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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unsigned Index = Idx->getZExtValue();
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SDValue ScalarOp = Node->getOperand(1);
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if (Index < NewNumElts_Lo)
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Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
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Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
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DAG.getIntPtrConstant(Index));
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else
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Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
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Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
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DAG.getIntPtrConstant(Index - NewNumElts_Lo));
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break;
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}
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@ -7519,7 +7519,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
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SDValue IdxNode = Mask.getOperand(i);
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if (IdxNode.getOpcode() == ISD::UNDEF) {
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Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
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Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
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continue;
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}
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unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
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@ -7528,16 +7528,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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InVec = Node->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
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Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
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Ops.clear();
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for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
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SDValue IdxNode = Mask.getOperand(i);
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if (IdxNode.getOpcode() == ISD::UNDEF) {
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Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
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Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
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continue;
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}
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unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
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@ -7546,20 +7546,20 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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InVec = Node->getOperand(1);
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Idx -= NumElements;
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}
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
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DAG.getConstant(Idx, PtrVT)));
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}
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Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
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Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
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break;
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}
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case ISD::BUILD_VECTOR: {
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SmallVector<SDValue, 8> LoOps(Node->op_begin(),
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Node->op_begin()+NewNumElts_Lo);
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Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
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Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
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SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
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Node->op_end());
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Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
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Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
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break;
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}
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case ISD::CONCAT_VECTORS: {
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@ -7571,11 +7571,13 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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} else {
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SmallVector<SDValue, 8> LoOps(Node->op_begin(),
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Node->op_begin()+NewNumSubvectors);
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Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
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Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
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&LoOps[0], LoOps.size());
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SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
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Node->op_end());
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Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
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Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
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&HiOps[0], HiOps.size());
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}
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break;
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}
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@ -7584,16 +7586,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue Idx = Op.getOperand(1);
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MVT IdxVT = Idx.getValueType();
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Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
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Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
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ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
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if (CIdx) {
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Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
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Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
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DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
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IdxVT));
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} else {
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Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
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Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
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DAG.getConstant(NewNumElts_Lo, IdxVT));
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Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
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Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
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}
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break;
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}
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@ -7608,12 +7610,12 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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// Handle a vector merge.
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SDValue CL, CH;
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SplitVectorOp(Cond, CL, CH);
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Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
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Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
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} else {
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// Handle a simple select with vector operands.
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Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
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Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
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}
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break;
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}
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@ -7627,9 +7629,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SplitVectorOp(Node->getOperand(3), RL, RH);
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// Handle a simple select with vector operands.
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Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
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Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
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LL, RL, CondCode);
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Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
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Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
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LH, RH, CondCode);
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break;
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}
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@ -7637,8 +7639,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue LL, LH, RL, RH;
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SplitVectorOp(Node->getOperand(0), LL, LH);
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SplitVectorOp(Node->getOperand(1), RL, RH);
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Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
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Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
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Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
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Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
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break;
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}
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case ISD::ADD:
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@ -7664,8 +7666,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SplitVectorOp(Node->getOperand(0), LL, LH);
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SplitVectorOp(Node->getOperand(1), RL, RH);
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Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
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Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
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Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
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break;
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}
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case ISD::FP_ROUND:
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@ -7673,8 +7675,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue L, H;
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SplitVectorOp(Node->getOperand(0), L, H);
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Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
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Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
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Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
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Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
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break;
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}
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case ISD::CTTZ:
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@ -7702,8 +7704,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue L, H;
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SplitVectorOp(Node->getOperand(0), L, H);
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Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
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Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
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Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
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Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
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break;
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}
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case ISD::CONVERT_RNDSAT: {
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@ -7736,27 +7738,27 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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bool isVolatile = LD->isVolatile();
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assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
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SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
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SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
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MVT MemNewEltVT = MemoryVT.getVectorElementType();
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MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
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MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
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Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
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Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
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NewVT_Lo, Ch, Ptr, Offset,
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SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
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unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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SVOffset += IncrementSize;
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Alignment = MinAlign(Alignment, IncrementSize);
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Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
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Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
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NewVT_Hi, Ch, Ptr, Offset,
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SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
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// Build a factor node to remember that this load is independent of the
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// other one.
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SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Remember that we legalized the chain.
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@ -7777,16 +7779,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
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int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
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SDValue St = DAG.getStore(DAG.getEntryNode(),
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SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
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InOp, Ptr,
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PseudoSourceValue::getFixedStack(FI), 0);
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InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
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InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
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PseudoSourceValue::getFixedStack(FI), 0);
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}
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// Split the vector and convert each of the pieces now.
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SplitVectorOp(InOp, Lo, Hi);
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Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
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Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
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break;
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}
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}
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@ -7805,6 +7807,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
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SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
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SDNode *Node = Op.getNode();
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DebugLoc dl = Node->getDebugLoc();
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MVT NewVT = Op.getValueType().getVectorElementType();
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assert(Op.getValueType().getVectorNumElements() == 1);
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@ -7835,7 +7838,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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Result = DAG.getNode(Node->getOpcode(),
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Result = DAG.getNode(Node->getOpcode(), dl,
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NewVT,
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ScalarizeVectorOp(Node->getOperand(0)),
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ScalarizeVectorOp(Node->getOperand(1)));
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@ -7859,7 +7862,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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case ISD::ANY_EXTEND:
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case ISD::TRUNCATE:
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case ISD::FP_EXTEND:
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Result = DAG.getNode(Node->getOpcode(),
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Result = DAG.getNode(Node->getOpcode(), dl,
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NewVT,
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ScalarizeVectorOp(Node->getOperand(0)));
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break;
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@ -7875,7 +7878,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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}
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case ISD::FPOWI:
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case ISD::FP_ROUND:
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Result = DAG.getNode(Node->getOpcode(),
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Result = DAG.getNode(Node->getOpcode(), dl,
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NewVT,
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ScalarizeVectorOp(Node->getOperand(0)),
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Node->getOperand(1));
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@ -7892,9 +7895,9 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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bool isVolatile = LD->isVolatile();
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assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
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SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
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SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
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Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
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Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
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NewVT, Ch, Ptr, Offset, SV, SVOffset,
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MemoryVT.getVectorElementType(),
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isVolatile, Alignment);
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@ -7925,23 +7928,23 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
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break;
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}
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case ISD::EXTRACT_SUBVECTOR:
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Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
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Node->getOperand(1));
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Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
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Node->getOperand(0), Node->getOperand(1));
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break;
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case ISD::BIT_CONVERT: {
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SDValue Op0 = Op.getOperand(0);
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if (Op0.getValueType().getVectorNumElements() == 1)
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Op0 = ScalarizeVectorOp(Op0);
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Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
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Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
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break;
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}
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case ISD::SELECT:
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Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
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Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
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ScalarizeVectorOp(Op.getOperand(1)),
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ScalarizeVectorOp(Op.getOperand(2)));
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break;
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case ISD::SELECT_CC:
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Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
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Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
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Node->getOperand(1),
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ScalarizeVectorOp(Op.getOperand(2)),
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ScalarizeVectorOp(Op.getOperand(3)),
|
||||
@ -7950,9 +7953,10 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
|
||||
case ISD::VSETCC: {
|
||||
SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
|
||||
SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
|
||||
Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
|
||||
Result = DAG.getNode(ISD::SETCC, dl,
|
||||
TLI.getSetCCResultType(Op0.getValueType()),
|
||||
Op0, Op1, Op.getOperand(2));
|
||||
Result = DAG.getNode(ISD::SELECT, NewVT, Result,
|
||||
Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
|
||||
DAG.getConstant(-1ULL, NewVT),
|
||||
DAG.getConstant(0ULL, NewVT));
|
||||
break;
|
||||
@ -7977,6 +7981,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
|
||||
SDValue Result;
|
||||
SDNode *Node = Op.getNode();
|
||||
DebugLoc dl = Node->getDebugLoc();
|
||||
MVT EVT = VT.getVectorElementType();
|
||||
|
||||
unsigned NumElts = VT.getVectorNumElements();
|
||||
@ -8012,20 +8017,21 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
assert(0 && "Unexpected operation in WidenVectorOp!");
|
||||
break;
|
||||
case ISD::UNDEF:
|
||||
Result = DAG.getNode(ISD::UNDEF, WidenVT);
|
||||
Result = DAG.getNode(ISD::UNDEF, dl, WidenVT);
|
||||
break;
|
||||
case ISD::BUILD_VECTOR: {
|
||||
// Build a vector with undefined for the new nodes
|
||||
SDValueVector NewOps(Node->op_begin(), Node->op_end());
|
||||
for (unsigned i = NumElts; i < NewNumElts; ++i) {
|
||||
NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
|
||||
NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT));
|
||||
}
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
|
||||
&NewOps[0], NewOps.size());
|
||||
break;
|
||||
}
|
||||
case ISD::INSERT_VECTOR_ELT: {
|
||||
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
|
||||
Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
|
||||
Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
|
||||
Node->getOperand(1), Node->getOperand(2));
|
||||
break;
|
||||
}
|
||||
@ -8054,14 +8060,14 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
}
|
||||
}
|
||||
for (unsigned i = NumElts; i < NewNumElts; ++i) {
|
||||
NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
|
||||
NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT));
|
||||
}
|
||||
|
||||
SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
|
||||
SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||
MVT::getVectorVT(PVT, NewOps.size()),
|
||||
&NewOps[0], NewOps.size());
|
||||
|
||||
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
|
||||
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
|
||||
break;
|
||||
}
|
||||
case ISD::LOAD: {
|
||||
@ -8090,7 +8096,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
|
||||
Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
|
||||
assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
|
||||
} else {
|
||||
// If the result size is a multiple of the input size, widen the input
|
||||
// and then convert.
|
||||
@ -8099,14 +8105,14 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
"can not widen bit convert that are not multiple of element type");
|
||||
unsigned NewNumElts = WidenSize / InSize;
|
||||
SmallVector<SDValue, 16> Ops(NewNumElts);
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
|
||||
Ops[0] = Tmp1;
|
||||
for (unsigned i = 1; i < NewNumElts; ++i)
|
||||
Ops[i] = UndefVal;
|
||||
|
||||
MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -8125,7 +8131,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
|
||||
Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
|
||||
assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -8148,7 +8154,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
SDValue Tmp1;
|
||||
Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
|
||||
assert(Tmp1.getValueType() == WidenVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
|
||||
break;
|
||||
}
|
||||
case ISD::CONVERT_RNDSAT: {
|
||||
@ -8198,7 +8204,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
|
||||
SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
|
||||
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -8213,14 +8219,14 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
WidenVT.getVectorNumElements());
|
||||
ShOp = WidenVectorOp(ShOp, NewShVT);
|
||||
assert(ShOp.getValueType() == NewShVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
|
||||
break;
|
||||
}
|
||||
|
||||
case ISD::EXTRACT_VECTOR_ELT: {
|
||||
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
|
||||
assert(Tmp1.getValueType() == WidenVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
|
||||
break;
|
||||
}
|
||||
case ISD::CONCAT_VECTORS: {
|
||||
@ -8228,13 +8234,13 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
// We could widen on a multiple of the incoming operand if necessary.
|
||||
unsigned NumConcat = NewNumElts / NumElts;
|
||||
assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
|
||||
SmallVector<SDValue, 8> MOps;
|
||||
MOps.push_back(Op);
|
||||
for (unsigned i = 1; i != NumConcat; ++i) {
|
||||
MOps.push_back(UndefVal);
|
||||
}
|
||||
Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
|
||||
Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
|
||||
&MOps[0], MOps.size()));
|
||||
break;
|
||||
}
|
||||
@ -8253,18 +8259,18 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
if (Tmp1VTNumElts < NewNumElts)
|
||||
Result = WidenVectorOp(Tmp1, WidenVT);
|
||||
else
|
||||
Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
|
||||
Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
|
||||
}
|
||||
} else if (NewNumElts % NumElts == 0) {
|
||||
// Widen the extracted subvector.
|
||||
unsigned NumConcat = NewNumElts / NumElts;
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
|
||||
SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
|
||||
SmallVector<SDValue, 8> MOps;
|
||||
MOps.push_back(Op);
|
||||
for (unsigned i = 1; i != NumConcat; ++i) {
|
||||
MOps.push_back(UndefVal);
|
||||
}
|
||||
Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
|
||||
Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
|
||||
&MOps[0], MOps.size()));
|
||||
} else {
|
||||
assert(0 && "can not widen extract subvector");
|
||||
@ -8287,7 +8293,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
|
||||
SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
|
||||
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -8309,7 +8315,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
|
||||
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
|
||||
"operands not widen");
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
|
||||
Tmp2, Node->getOperand(4));
|
||||
break;
|
||||
}
|
||||
@ -8322,7 +8328,7 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
|
||||
Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
|
||||
SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
|
||||
Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
|
||||
Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
|
||||
Node->getOperand(2));
|
||||
break;
|
||||
}
|
||||
@ -8389,7 +8395,8 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
||||
unsigned Alignment,
|
||||
bool isVolatile,
|
||||
unsigned LdWidth,
|
||||
MVT ResType) {
|
||||
MVT ResType,
|
||||
DebugLoc dl) {
|
||||
// We assume that we have good rules to handle loading power of two loads so
|
||||
// we break down the operations to power of 2 loads. The strategy is to
|
||||
// load the largest power of 2 that we can easily transform to a legal vector
|
||||
@ -8403,14 +8410,14 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
||||
FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
|
||||
EVTWidth = EVT.getSizeInBits();
|
||||
|
||||
SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
|
||||
SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
|
||||
isVolatile, Alignment);
|
||||
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
|
||||
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
|
||||
LdChain.push_back(LdOp.getValue(1));
|
||||
|
||||
// Check if we can load the element with one instruction
|
||||
if (LdWidth == EVTWidth) {
|
||||
return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
|
||||
return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
|
||||
}
|
||||
|
||||
// The vector element order is endianness dependent.
|
||||
@ -8421,7 +8428,7 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
||||
while (LdWidth > 0) {
|
||||
unsigned Increment = EVTWidth / 8;
|
||||
Offset += Increment;
|
||||
BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
|
||||
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
|
||||
DAG.getIntPtrConstant(Increment));
|
||||
|
||||
if (LdWidth < EVTWidth) {
|
||||
@ -8432,20 +8439,20 @@ SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
|
||||
EVTWidth = EVT.getSizeInBits();
|
||||
// Readjust position and vector position based on new load type
|
||||
Idx = Idx * (oEVTWidth/EVTWidth);
|
||||
VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
|
||||
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
|
||||
}
|
||||
|
||||
SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
|
||||
SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
|
||||
SVOffset+Offset, isVolatile,
|
||||
MinAlign(Alignment, Offset));
|
||||
LdChain.push_back(LdOp.getValue(1));
|
||||
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
|
||||
VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
|
||||
DAG.getIntPtrConstant(Idx++));
|
||||
|
||||
LdWidth -= EVTWidth;
|
||||
}
|
||||
|
||||
return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
|
||||
return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
|
||||
}
|
||||
|
||||
bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
|
||||
@ -8461,6 +8468,7 @@ bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
|
||||
// we need to load from.
|
||||
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
|
||||
MVT LdVT = LD->getMemoryVT();
|
||||
DebugLoc dl = LD->getDebugLoc();
|
||||
assert(LdVT.isVector() && NVT.isVector());
|
||||
assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
|
||||
|
||||
@ -8476,14 +8484,15 @@ bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
|
||||
// Load value as a large register
|
||||
SDValueVector LdChain;
|
||||
Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
|
||||
Alignment, isVolatile, LdWidth, NVT);
|
||||
Alignment, isVolatile, LdWidth, NVT, dl);
|
||||
|
||||
if (LdChain.size() == 1) {
|
||||
TFOp = LdChain[0];
|
||||
return true;
|
||||
}
|
||||
else {
|
||||
TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
|
||||
TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||
&LdChain[0], LdChain.size());
|
||||
return false;
|
||||
}
|
||||
}
|
||||
@ -8497,7 +8506,8 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
||||
unsigned Alignment,
|
||||
bool isVolatile,
|
||||
SDValue ValOp,
|
||||
unsigned StWidth) {
|
||||
unsigned StWidth,
|
||||
DebugLoc dl) {
|
||||
// Breaks the stores into a series of power of 2 width stores. For any
|
||||
// width, we convert the vector to the vector of element size that we
|
||||
// want to store. This avoids requiring a stack convert.
|
||||
@ -8509,10 +8519,10 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
||||
FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
|
||||
EVTWidth = EVT.getSizeInBits();
|
||||
|
||||
SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
|
||||
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
|
||||
SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
|
||||
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
|
||||
DAG.getIntPtrConstant(0));
|
||||
SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
|
||||
SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
|
||||
isVolatile, Alignment);
|
||||
StChain.push_back(StOp);
|
||||
|
||||
@ -8528,7 +8538,7 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
||||
while (StWidth > 0) {
|
||||
unsigned Increment = EVTWidth / 8;
|
||||
Offset += Increment;
|
||||
BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
|
||||
BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
|
||||
DAG.getIntPtrConstant(Increment));
|
||||
|
||||
if (StWidth < EVTWidth) {
|
||||
@ -8539,12 +8549,12 @@ void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
|
||||
EVTWidth = EVT.getSizeInBits();
|
||||
// Readjust position and vector position based on new load type
|
||||
Idx = Idx * (oEVTWidth/EVTWidth);
|
||||
VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
|
||||
VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
|
||||
}
|
||||
|
||||
EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
|
||||
EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
|
||||
DAG.getIntPtrConstant(Idx++));
|
||||
StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
|
||||
StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
|
||||
SVOffset + Offset, isVolatile,
|
||||
MinAlign(Alignment, Offset)));
|
||||
StWidth -= EVTWidth;
|
||||
@ -8563,6 +8573,7 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
|
||||
|
||||
MVT StVT = ST->getMemoryVT();
|
||||
SDValue ValOp = ST->getValue();
|
||||
DebugLoc dl = ST->getDebugLoc();
|
||||
|
||||
// Check if we have widen this node with another value
|
||||
std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
|
||||
@ -8581,11 +8592,12 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
|
||||
SDValueVector StChain;
|
||||
genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
|
||||
ST->getSrcValueOffset(), ST->getAlignment(),
|
||||
ST->isVolatile(), ValOp, StVT.getSizeInBits());
|
||||
ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
|
||||
if (StChain.size() == 1)
|
||||
return StChain[0];
|
||||
else
|
||||
return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
|
||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||
&StChain[0], StChain.size());
|
||||
}
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user