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Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
eef965f04b
commit
c6df9883da
@ -42,7 +42,8 @@ X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
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}
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void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
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printInstruction(MI, OS);
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if (printAliasInstr(MI, OS))
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printInstruction(MI, OS);
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// If verbose assembly is enabled, we can print some informative comments.
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if (CommentStream)
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@ -1437,7 +1437,7 @@ def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
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// Various unary fpstack operations default to operating on on ST1.
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// For example, "fxch" -> "fxch %st(1)"
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def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
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def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
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def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
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def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
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def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
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@ -1455,13 +1455,15 @@ def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
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// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
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// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
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// gas.
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multiclass FpUnaryAlias<string Mnemonic, Instruction Inst> {
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def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), (Inst RST:$op)>;
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def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), (Inst ST0)>;
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multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
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def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
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(Inst RST:$op), EmitAlias>;
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def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
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(Inst ST0), EmitAlias>;
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}
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defm : FpUnaryAlias<"fadd", ADD_FST0r>;
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defm : FpUnaryAlias<"faddp", ADD_FPrST0>;
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defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
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defm : FpUnaryAlias<"fsub", SUB_FST0r>;
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defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
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defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
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@ -1472,8 +1474,8 @@ defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
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defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
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defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
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defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
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defm : FpUnaryAlias<"fcomi", COM_FIr>;
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defm : FpUnaryAlias<"fucomi", UCOM_FIr>;
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defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
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defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
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defm : FpUnaryAlias<"fcompi", COM_FIPr>;
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defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
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@ -1481,7 +1483,7 @@ defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
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// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
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// commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
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// solely because gas supports it.
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def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op)>;
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def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
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def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
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def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
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def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
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@ -1535,9 +1537,9 @@ def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
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// Match 'movq GR64, MMX' as an alias for movd.
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def : InstAlias<"movq $src, $dst",
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(MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0b0>;
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(MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
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def : InstAlias<"movq $src, $dst",
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(MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0b0>;
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(MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
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// movsd with no operands (as opposed to the SSE scalar move of a double) is an
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// alias for movsl. (as in rep; movsd)
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@ -1,6 +1,6 @@
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; RUN: llc < %s -march=x86-64 > %t
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; RUN: grep movb %t | count 2
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; RUN: grep {movzb\[wl\]} %t
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; RUN: grep {movzx} %t
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define void @handle_vector_size_attribute() nounwind {
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86 | grep {movsbl}
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; RUN: llc < %s -march=x86 | grep {movsx}
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@X = global i32 0 ; <i32*> [#uses=1]
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@ -22,8 +22,8 @@ entry:
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; CHECK: bar:
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; CHECK: fldt 4(%esp)
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; CHECK-NEXT: fld %st(0)
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; CHECK-NEXT: fmul %st(1)
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; CHECK-NEXT: fmulp %st(1)
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; CHECK-NEXT: fmul %st(1), %st(0)
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; CHECK-NEXT: fmulp
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; CHECK-NEXT: ret
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}
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@ -1,9 +1,10 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
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entry:
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tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
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ret i32 %0
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; CHECK: movzx
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tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
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ret i32 %0
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}
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declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
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@ -1,9 +1,8 @@
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; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
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; RUN: grep movzwl %t1 | count 2
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; RUN: grep movzbl %t1 | count 2
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; RUN: grep movd %t1 | count 4
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; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s
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define <4 x i16> @a(i32* %x1) nounwind {
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; CHECK: movzx
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; CHECK-NEXT: movd
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%x2 = load i32* %x1
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%x3 = lshr i32 %x2, 1
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%x = trunc i32 %x3 to i16
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@ -12,6 +11,8 @@ define <4 x i16> @a(i32* %x1) nounwind {
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}
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define <8 x i16> @b(i32* %x1) nounwind {
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; CHECK: movzx
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; CHECK-NEXT: movd
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%x2 = load i32* %x1
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%x3 = lshr i32 %x2, 1
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%x = trunc i32 %x3 to i16
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@ -20,6 +21,8 @@ define <8 x i16> @b(i32* %x1) nounwind {
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}
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define <8 x i8> @c(i32* %x1) nounwind {
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; CHECK: movzx
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; CHECK-NEXT: movd
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%x2 = load i32* %x1
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%x3 = lshr i32 %x2, 1
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%x = trunc i32 %x3 to i8
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@ -28,6 +31,8 @@ define <8 x i8> @c(i32* %x1) nounwind {
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}
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define <16 x i8> @d(i32* %x1) nounwind {
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; CHECK: movzx
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; CHECK-NEXT: movd
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%x2 = load i32* %x1
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%x3 = lshr i32 %x2, 1
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%x = trunc i32 %x3 to i8
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@ -1,8 +1,10 @@
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; RUN: llc < %s -march=x86-64 | grep movzbl | count 2
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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; Use movzbl to avoid partial-register updates.
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; Use movzbl (aliased as movzx) to avoid partial-register updates.
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define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
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; CHECK: movzx %dil, %eax
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; CHECK: movzx %al, %eax
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%q = trunc i32 %p to i8
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%r = udiv i8 %q, %x
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%s = zext i8 %r to i32
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@ -75,7 +75,7 @@ declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounw
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define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vcomisd
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; CHECK: sete
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -85,7 +85,7 @@ declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readno
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define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vcomisd
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; CHECK: setae
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -95,7 +95,7 @@ declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readno
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define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vcomisd
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; CHECK: seta
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -105,7 +105,7 @@ declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readno
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define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vcomisd
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; CHECK: setbe
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -125,7 +125,7 @@ declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readno
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define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vcomisd
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; CHECK: setne
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -786,7 +786,7 @@ declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>) nounwind
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define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vucomisd
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; CHECK: sete
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -796,7 +796,7 @@ declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readn
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define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vucomisd
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; CHECK: setae
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -806,7 +806,7 @@ declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readn
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define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vucomisd
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; CHECK: seta
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -816,7 +816,7 @@ declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readn
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define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vucomisd
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; CHECK: setbe
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -835,7 +835,7 @@ declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readn
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define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vucomisd
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; CHECK: setne
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1192,7 +1192,7 @@ declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse41_ptestnzc(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vptest
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; CHECK: seta
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1202,7 +1202,7 @@ declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse41_ptestz(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vptest
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; CHECK: sete
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1414,7 +1414,7 @@ declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind
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define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vcomiss
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; CHECK: sete
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1424,7 +1424,7 @@ declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vcomiss
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; CHECK: setae
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1434,7 +1434,7 @@ declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vcomiss
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; CHECK: seta
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1444,7 +1444,7 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vcomiss
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; CHECK: setbe
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
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@ -1463,7 +1463,7 @@ declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>) nounwind readnone
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define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vcomiss
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; CHECK: setne
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; CHECK: movzbl
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; CHECK: movzx
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%res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
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ret i32 %res
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}
|
||||
@ -1655,7 +1655,7 @@ declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind read
|
||||
define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vucomiss
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -1665,7 +1665,7 @@ declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>) nounwind readnone
|
||||
define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vucomiss
|
||||
; CHECK: setae
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -1675,7 +1675,7 @@ declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
|
||||
define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vucomiss
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -1685,7 +1685,7 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>) nounwind readnone
|
||||
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vucomiss
|
||||
; CHECK: setbe
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -1704,7 +1704,7 @@ declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>) nounwind readnone
|
||||
define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vucomiss
|
||||
; CHECK: setne
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2179,7 +2179,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
|
||||
define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
|
||||
; CHECK: vptest
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2189,7 +2189,7 @@ declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone
|
||||
define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
|
||||
; CHECK: vptest
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2483,7 +2483,7 @@ declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readn
|
||||
define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; CHECK: vtestpd
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2493,7 +2493,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readn
|
||||
define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
||||
; CHECK: vtestpd
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2503,7 +2503,7 @@ declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind r
|
||||
define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vtestps
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2513,7 +2513,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnon
|
||||
define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
||||
; CHECK: vtestps
|
||||
; CHECK: seta
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2523,7 +2523,7 @@ declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind rea
|
||||
define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; CHECK: vtestpd
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2533,7 +2533,7 @@ declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnon
|
||||
define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
||||
; CHECK: vtestpd
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2543,7 +2543,7 @@ declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind rea
|
||||
define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vtestps
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
@ -2553,7 +2553,7 @@ declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
|
||||
define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
||||
; CHECK: vtestps
|
||||
; CHECK: sete
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
%res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; RUN: llc < %s -march=x86-64 | FileCheck %s
|
||||
|
||||
; CHECK: @bar1
|
||||
; CHECK: movzbl
|
||||
; CHECK: movzx
|
||||
; CHECK: callq
|
||||
define void @bar1(i1 zeroext %v1) nounwind ssp {
|
||||
entry:
|
||||
@ -11,7 +11,7 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK: @bar2
|
||||
; CHECK-NOT: movzbl
|
||||
; CHECK-NOT: movzx
|
||||
; CHECK: callq
|
||||
define void @bar2(i8 zeroext %v1) nounwind ssp {
|
||||
entry:
|
||||
@ -22,7 +22,7 @@ entry:
|
||||
|
||||
; CHECK: @bar3
|
||||
; CHECK: callq
|
||||
; CHECK-NOT: movzbl
|
||||
; CHECK-NOT: movzx
|
||||
; CHECK-NOT: and
|
||||
; CHECK: ret
|
||||
define zeroext i1 @bar3() nounwind ssp {
|
||||
|
||||
@ -121,7 +121,7 @@ define i32 @test5(i32* nocapture %P) nounwind readonly {
|
||||
entry:
|
||||
; CHECK: test5:
|
||||
; CHECK: setg %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: orl $-2, %eax
|
||||
; CHECK: ret
|
||||
|
||||
@ -135,7 +135,7 @@ define i32 @test6(i32* nocapture %P) nounwind readonly {
|
||||
entry:
|
||||
; CHECK: test6:
|
||||
; CHECK: setl %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: leal 4(%rax,%rax,8), %eax
|
||||
; CHECK: ret
|
||||
%0 = load i32* %P, align 4 ; <i32> [#uses=1]
|
||||
|
||||
@ -38,7 +38,7 @@ define i64 @test3(i64 %x) nounwind {
|
||||
; CHECK: test3:
|
||||
; CHECK: testq %rdi, %rdi
|
||||
; CHECK: sete %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
@ -49,7 +49,7 @@ define i64 @test4(i64 %x) nounwind {
|
||||
; CHECK: test4:
|
||||
; CHECK: testq %rdi, %rdi
|
||||
; CHECK: setle %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
|
||||
@ -14,7 +14,7 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
|
||||
; X32: ret
|
||||
|
||||
; X64: test1:
|
||||
; X64: movslq %e[[A0:di|cx]], %rax
|
||||
; X64: movsx %e[[A0:di|cx]], %rax
|
||||
; X64: movl (%r[[A1:si|dx]],%rax,4), %eax
|
||||
; X64: ret
|
||||
|
||||
@ -81,7 +81,7 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
|
||||
%v11 = add i64 %B, %v10
|
||||
ret i64 %v11
|
||||
; X64: test5:
|
||||
; X64: movslq %e[[A1]], %rax
|
||||
; X64: movsx %e[[A1]], %rax
|
||||
; X64-NEXT: movq (%r[[A0]],%rax), %rax
|
||||
; X64-NEXT: addq %{{rdx|r8}}, %rax
|
||||
; X64-NEXT: ret
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
; RUN: llc < %s -march=x86 -mcpu=i386 | grep {fucompi.*st.\[12\]}
|
||||
; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s
|
||||
; PR1012
|
||||
|
||||
define float @foo(float* %col.2.0) {
|
||||
%tmp = load float* %col.2.0 ; <float> [#uses=3]
|
||||
%tmp16 = fcmp olt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
|
||||
%tmp20 = fsub float -0.000000e+00, %tmp ; <float> [#uses=1]
|
||||
%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp ; <float> [#uses=1]
|
||||
ret float %iftmp.2.0
|
||||
; CHECK: fucompi
|
||||
%tmp = load float* %col.2.0
|
||||
%tmp16 = fcmp olt float %tmp, 0.000000e+00
|
||||
%tmp20 = fsub float -0.000000e+00, %tmp
|
||||
%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
|
||||
ret float %iftmp.2.0
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
|
||||
; RUN: llc < %s -march=x86 | grep {movzx %\[abcd\]h,} | count 7
|
||||
|
||||
; Use h-register extract and zero-extend.
|
||||
|
||||
|
||||
@ -70,7 +70,7 @@ define i64 @qux64(i64 inreg %x) nounwind {
|
||||
; WIN64: movzbl %ch, %eax
|
||||
|
||||
; X86-32: qux64:
|
||||
; X86-32: movzbl %ah, %eax
|
||||
; X86-32: movzx %ah, %eax
|
||||
%t0 = lshr i64 %x, 8
|
||||
%t1 = and i64 %t0, 255
|
||||
ret i64 %t1
|
||||
@ -85,7 +85,7 @@ define i32 @qux32(i32 inreg %x) nounwind {
|
||||
; WIN64: movzbl %ch, %eax
|
||||
|
||||
; X86-32: qux32:
|
||||
; X86-32: movzbl %ah, %eax
|
||||
; X86-32: movzx %ah, %eax
|
||||
%t0 = lshr i32 %x, 8
|
||||
%t1 = and i32 %t0, 255
|
||||
ret i32 %t1
|
||||
@ -100,7 +100,7 @@ define i16 @qux16(i16 inreg %x) nounwind {
|
||||
; WIN64: movzbl %ch, %eax
|
||||
|
||||
; X86-32: qux16:
|
||||
; X86-32: movzbl %ah, %eax
|
||||
; X86-32: movzx %ah, %eax
|
||||
%t0 = lshr i16 %x, 8
|
||||
ret i16 %t0
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc < %s -march=x86 > %t
|
||||
; RUN: grep {movzbl %\[abcd\]h,} %t | count 1
|
||||
; RUN: grep {movzx %\[abcd\]h,} %t | count 1
|
||||
; RUN: grep {shll \$3,} %t | count 1
|
||||
|
||||
; Use an h register, but don't omit the explicit shift for
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; PR2094
|
||||
; RUN: llc < %s -march=x86-64 | grep movslq
|
||||
; RUN: llc < %s -march=x86-64 | grep movsx
|
||||
; RUN: llc < %s -march=x86-64 | grep addps
|
||||
; RUN: llc < %s -march=x86-64 | grep paddd
|
||||
; RUN: llc < %s -march=x86-64 | not grep movq
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -march=x86-64 > %t
|
||||
; RUN: grep and %t | count 6
|
||||
; RUN: grep movzb %t | count 6
|
||||
; RUN: grep movzx %t | count 6
|
||||
; RUN: grep sar %t | count 12
|
||||
|
||||
; Don't optimize away zext-inreg and sext-inreg on the loop induction
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
|
||||
; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s
|
||||
; PR3366
|
||||
|
||||
; CHECK: movzx
|
||||
define void @_ada_c34002a() nounwind {
|
||||
entry:
|
||||
%0 = load i8* null, align 1
|
||||
|
||||
@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin11"
|
||||
; ISel doesn't yet know how to eliminate this extra zero-extend. But until
|
||||
; it knows how to do so safely, it shouldn;t eliminate it.
|
||||
; CHECK: movzbl (%rdi), %eax
|
||||
; CHECK: movzwl %ax, %eax
|
||||
; CHECK: movzx %ax, %eax
|
||||
|
||||
define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
|
||||
entry:
|
||||
|
||||
@ -4,8 +4,8 @@ define signext i16 @foo(i16 signext %x) nounwind {
|
||||
entry:
|
||||
; CHECK: foo:
|
||||
; CHECK: movzwl 4(%esp), %eax
|
||||
; CHECK: xorl $21998, %eax
|
||||
; CHECK: movswl %ax, %eax
|
||||
; CHECK: xorl $21998, %eax
|
||||
; CHECK: movsx %ax, %eax
|
||||
%0 = xor i16 %x, 21998
|
||||
ret i16 %0
|
||||
}
|
||||
|
||||
@ -30,7 +30,7 @@ bb91: ; preds = %bb84
|
||||
ret i32 0
|
||||
; CHECK: test2:
|
||||
; CHECK: movnew
|
||||
; CHECK: movswl
|
||||
; CHECK: movsx
|
||||
}
|
||||
|
||||
declare i1 @return_false()
|
||||
|
||||
@ -8,7 +8,7 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
|
||||
entry:
|
||||
; CHECK: t1:
|
||||
; CHECK: seta %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: shll $5, %eax
|
||||
%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
|
||||
%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=x86 | grep movzbl | count 1
|
||||
; RUN: llc < %s -march=x86 | grep movzx | count 1
|
||||
; rdar://6699246
|
||||
|
||||
define signext i8 @t1(i8* %A) nounwind readnone ssp {
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
|
||||
; CHECK: t:
|
||||
; CHECK: movslq %e{{.*}}, %rax
|
||||
; CHECK: movsx %e{{.*}}, %rax
|
||||
; CHECK: movq %rax
|
||||
; CHECK: movl %eax
|
||||
%C = add i64 %A, %B
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
|
||||
; RUN: llc < %s -march=x86 | grep {shrl .eax}
|
||||
; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
|
||||
; RUN: llc < %s -march=x86 | grep {movsx .ax, .eax}
|
||||
|
||||
define i32 @test1(i64 %a) nounwind {
|
||||
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
|
||||
|
||||
@ -9,6 +9,6 @@ define i1 @a(i32 %x) zeroext nounwind {
|
||||
; CHECK: a:
|
||||
; CHECK: mull
|
||||
; CHECK: seto %al
|
||||
; CHECK: movzbl %al, %eax
|
||||
; CHECK: movzx %al, %eax
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
@ -57,7 +57,7 @@ entry:
|
||||
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
|
||||
entry:
|
||||
; CHECK: shift3a:
|
||||
; CHECK: movzwl
|
||||
; CHECK: movzx
|
||||
; CHECK: psllw
|
||||
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
|
||||
%shl = shl <8 x i16> %val, %shamt
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
|
||||
; CHECK: movswl
|
||||
; CHECK: movswl
|
||||
; CHECK: movsx
|
||||
; CHECK: movsx
|
||||
|
||||
; sign extension v2i32 to v2i16
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s | grep movswl
|
||||
; RUN: llc < %s | grep movsx
|
||||
|
||||
target datalayout = "e-p:64:64"
|
||||
target triple = "x86_64-apple-darwin8"
|
||||
|
||||
@ -613,11 +613,11 @@ pshufw $90, %mm4, %mm0
|
||||
// CHECK: encoding: [0xd5,0x01]
|
||||
aad $1
|
||||
|
||||
// CHECK: aad $10
|
||||
// CHECK: aad
|
||||
// CHECK: encoding: [0xd5,0x0a]
|
||||
aad $0xA
|
||||
|
||||
// CHECK: aad $10
|
||||
// CHECK: aad
|
||||
// CHECK: encoding: [0xd5,0x0a]
|
||||
aad
|
||||
|
||||
@ -625,11 +625,11 @@ pshufw $90, %mm4, %mm0
|
||||
// CHECK: encoding: [0xd4,0x02]
|
||||
aam $2
|
||||
|
||||
// CHECK: aam $10
|
||||
// CHECK: aam
|
||||
// CHECK: encoding: [0xd4,0x0a]
|
||||
aam $0xA
|
||||
|
||||
// CHECK: aam $10
|
||||
// CHECK: aam
|
||||
// CHECK: encoding: [0xd4,0x0a]
|
||||
aam
|
||||
|
||||
@ -725,7 +725,7 @@ pshufw $90, %mm4, %mm0
|
||||
// CHECK: encoding: [0xdf,0xf2]
|
||||
fcompi %st(2)
|
||||
|
||||
// CHECK: fcompi %st(1)
|
||||
// CHECK: fcompi
|
||||
// CHECK: encoding: [0xdf,0xf1]
|
||||
fcompi
|
||||
|
||||
@ -737,7 +737,7 @@ pshufw $90, %mm4, %mm0
|
||||
// CHECK: encoding: [0xdf,0xea]
|
||||
fucompi %st(2)
|
||||
|
||||
// CHECK: fucompi %st(1)
|
||||
// CHECK: fucompi
|
||||
// CHECK: encoding: [0xdf,0xe9]
|
||||
fucompi
|
||||
|
||||
@ -866,9 +866,9 @@ pshufw $90, %mm4, %mm0
|
||||
movsw %ds:(%esi), %es:(%edi)
|
||||
movsw (%esi), %es:(%edi)
|
||||
|
||||
// CHECK: movsl # encoding: [0xa5]
|
||||
// CHECK: movsl
|
||||
// CHECK: movsl
|
||||
// CHECK: movsd # encoding: [0xa5]
|
||||
// CHECK: movsd
|
||||
// CHECK: movsd
|
||||
movsl
|
||||
movsl %ds:(%esi), %es:(%edi)
|
||||
movsl (%esi), %es:(%edi)
|
||||
|
||||
@ -112,12 +112,12 @@
|
||||
// rdar://8470918
|
||||
smovb // CHECK: movsb
|
||||
smovw // CHECK: movsw
|
||||
smovl // CHECK: movsl
|
||||
smovl // CHECK: movsd
|
||||
smovq // CHECK: movsq
|
||||
|
||||
// rdar://8456361
|
||||
// CHECK: rep
|
||||
// CHECK: movsl
|
||||
// CHECK: movsd
|
||||
rep movsd
|
||||
|
||||
// CHECK: rep
|
||||
@ -232,10 +232,10 @@ cmovnzq %rbx, %rax
|
||||
|
||||
// rdar://8407928
|
||||
// CHECK: inb $127, %al
|
||||
// CHECK: inw %dx, %ax
|
||||
// CHECK: inw %dx
|
||||
// CHECK: outb %al, $127
|
||||
// CHECK: outw %ax, %dx
|
||||
// CHECK: inl %dx, %eax
|
||||
// CHECK: outw %dx
|
||||
// CHECK: inl %dx
|
||||
inb $0x7f
|
||||
inw %dx
|
||||
outb $0x7f
|
||||
@ -244,12 +244,12 @@ inl %dx
|
||||
|
||||
|
||||
// PR8114
|
||||
// CHECK: outb %al, %dx
|
||||
// CHECK: outb %al, %dx
|
||||
// CHECK: outw %ax, %dx
|
||||
// CHECK: outw %ax, %dx
|
||||
// CHECK: outl %eax, %dx
|
||||
// CHECK: outl %eax, %dx
|
||||
// CHECK: outb %dx
|
||||
// CHECK: outb %dx
|
||||
// CHECK: outw %dx
|
||||
// CHECK: outw %dx
|
||||
// CHECK: outl %dx
|
||||
// CHECK: outl %dx
|
||||
|
||||
out %al, (%dx)
|
||||
outb %al, (%dx)
|
||||
@ -258,12 +258,12 @@ outw %ax, (%dx)
|
||||
out %eax, (%dx)
|
||||
outl %eax, (%dx)
|
||||
|
||||
// CHECK: inb %dx, %al
|
||||
// CHECK: inb %dx, %al
|
||||
// CHECK: inw %dx, %ax
|
||||
// CHECK: inw %dx, %ax
|
||||
// CHECK: inl %dx, %eax
|
||||
// CHECK: inl %dx, %eax
|
||||
// CHECK: inb %dx
|
||||
// CHECK: inb %dx
|
||||
// CHECK: inw %dx
|
||||
// CHECK: inw %dx
|
||||
// CHECK: inl %dx
|
||||
// CHECK: inl %dx
|
||||
|
||||
in (%dx), %al
|
||||
inb (%dx), %al
|
||||
@ -274,16 +274,16 @@ inl (%dx), %eax
|
||||
|
||||
// rdar://8431422
|
||||
|
||||
// CHECK: fxch %st(1)
|
||||
// CHECK: fucom %st(1)
|
||||
// CHECK: fucomp %st(1)
|
||||
// CHECK: faddp %st(1)
|
||||
// CHECK: fxch
|
||||
// CHECK: fucom
|
||||
// CHECK: fucomp
|
||||
// CHECK: faddp
|
||||
// CHECK: faddp %st(0)
|
||||
// CHECK: fsubp %st(1)
|
||||
// CHECK: fsubrp %st(1)
|
||||
// CHECK: fmulp %st(1)
|
||||
// CHECK: fdivp %st(1)
|
||||
// CHECK: fdivrp %st(1)
|
||||
// CHECK: fsubp
|
||||
// CHECK: fsubrp
|
||||
// CHECK: fmulp
|
||||
// CHECK: fdivp
|
||||
// CHECK: fdivrp
|
||||
|
||||
fxch
|
||||
fucom
|
||||
@ -296,11 +296,11 @@ fmulp
|
||||
fdivp
|
||||
fdivrp
|
||||
|
||||
// CHECK: fcomi %st(1)
|
||||
// CHECK: fcomi
|
||||
// CHECK: fcomi %st(2)
|
||||
// CHECK: fucomi %st(1)
|
||||
// CHECK: fucomi %st(2)
|
||||
// CHECK: fucomi %st(2)
|
||||
// CHECK: fucomi
|
||||
// CHECK: fucomi %st(2)
|
||||
// CHECK: fucomi %st(2)
|
||||
|
||||
fcomi
|
||||
fcomi %st(2)
|
||||
@ -604,7 +604,7 @@ movsq
|
||||
// CHECK: encoding: [0x48,0xa5]
|
||||
|
||||
movsl
|
||||
// CHECK: movsl
|
||||
// CHECK: movsd
|
||||
// CHECK: encoding: [0xa5]
|
||||
|
||||
stosq
|
||||
@ -681,65 +681,65 @@ btq $0x01,%rdx
|
||||
// CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01]
|
||||
|
||||
//rdar://8017633
|
||||
// CHECK: movzbl %al, %esi
|
||||
// CHECK: movzx %al, %esi
|
||||
// CHECK: encoding: [0x0f,0xb6,0xf0]
|
||||
movzx %al, %esi
|
||||
|
||||
// CHECK: movzbq %al, %rsi
|
||||
// CHECK: movzx %al, %rsi
|
||||
// CHECK: encoding: [0x48,0x0f,0xb6,0xf0]
|
||||
movzx %al, %rsi
|
||||
|
||||
// CHECK: movsbw %al, %ax
|
||||
// CHECK: movsx %al, %ax
|
||||
// CHECK: encoding: [0x66,0x0f,0xbe,0xc0]
|
||||
movsx %al, %ax
|
||||
movsx %al, %ax
|
||||
|
||||
// CHECK: movsbl %al, %eax
|
||||
// CHECK: movsx %al, %eax
|
||||
// CHECK: encoding: [0x0f,0xbe,0xc0]
|
||||
movsx %al, %eax
|
||||
movsx %al, %eax
|
||||
|
||||
// CHECK: movswl %ax, %eax
|
||||
// CHECK: movsx %ax, %eax
|
||||
// CHECK: encoding: [0x0f,0xbf,0xc0]
|
||||
movsx %ax, %eax
|
||||
movsx %ax, %eax
|
||||
|
||||
// CHECK: movsbq %bl, %rax
|
||||
// CHECK: movsx %bl, %rax
|
||||
// CHECK: encoding: [0x48,0x0f,0xbe,0xc3]
|
||||
movsx %bl, %rax
|
||||
movsx %bl, %rax
|
||||
|
||||
// CHECK: movswq %cx, %rax
|
||||
// CHECK: movsx %cx, %rax
|
||||
// CHECK: encoding: [0x48,0x0f,0xbf,0xc1]
|
||||
movsx %cx, %rax
|
||||
movsx %cx, %rax
|
||||
|
||||
// CHECK: movslq %edi, %rax
|
||||
// CHECK: movsx %edi, %rax
|
||||
// CHECK: encoding: [0x48,0x63,0xc7]
|
||||
movsx %edi, %rax
|
||||
movsx %edi, %rax
|
||||
|
||||
// CHECK: movzbw %al, %ax
|
||||
// CHECK: movzx %al, %ax
|
||||
// CHECK: encoding: [0x66,0x0f,0xb6,0xc0]
|
||||
movzx %al, %ax
|
||||
movzx %al, %ax
|
||||
|
||||
// CHECK: movzbl %al, %eax
|
||||
// CHECK: movzx %al, %eax
|
||||
// CHECK: encoding: [0x0f,0xb6,0xc0]
|
||||
movzx %al, %eax
|
||||
movzx %al, %eax
|
||||
|
||||
// CHECK: movzwl %ax, %eax
|
||||
// CHECK: movzx %ax, %eax
|
||||
// CHECK: encoding: [0x0f,0xb7,0xc0]
|
||||
movzx %ax, %eax
|
||||
movzx %ax, %eax
|
||||
|
||||
// CHECK: movzbq %bl, %rax
|
||||
// CHECK: movzx %bl, %rax
|
||||
// CHECK: encoding: [0x48,0x0f,0xb6,0xc3]
|
||||
movzx %bl, %rax
|
||||
movzx %bl, %rax
|
||||
|
||||
// CHECK: movzwq %cx, %rax
|
||||
// CHECK: movzx %cx, %rax
|
||||
// CHECK: encoding: [0x48,0x0f,0xb7,0xc1]
|
||||
movzx %cx, %rax
|
||||
movzx %cx, %rax
|
||||
|
||||
// CHECK: movsbw (%rax), %ax
|
||||
// CHECK: encoding: [0x66,0x0f,0xbe,0x00]
|
||||
movsx (%rax), %ax
|
||||
movsx (%rax), %ax
|
||||
|
||||
// CHECK: movzbw (%rax), %ax
|
||||
// CHECK: encoding: [0x66,0x0f,0xb6,0x00]
|
||||
movzx (%rax), %ax
|
||||
movzx (%rax), %ax
|
||||
|
||||
|
||||
// rdar://7873482
|
||||
@ -790,7 +790,7 @@ lock/incl 1(%rsp)
|
||||
rep movsl
|
||||
// CHECK: rep
|
||||
// CHECK: encoding: [0xf3]
|
||||
// CHECK: movsl
|
||||
// CHECK: movsd
|
||||
// CHECK: encoding: [0xa5]
|
||||
|
||||
|
||||
@ -1027,9 +1027,9 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
|
||||
movsw %ds:(%rsi), %es:(%rdi)
|
||||
movsw (%rsi), %es:(%rdi)
|
||||
|
||||
// CHECK: movsl # encoding: [0xa5]
|
||||
// CHECK: movsl
|
||||
// CHECK: movsl
|
||||
// CHECK: movsd # encoding: [0xa5]
|
||||
// CHECK: movsd
|
||||
// CHECK: movsd
|
||||
movsl
|
||||
movsl %ds:(%rsi), %es:(%rdi)
|
||||
movsl (%rsi), %es:(%rdi)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user