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ARM stm/ldm instructions require more than one register in the register list.

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Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-12-09 18:31:13 +00:00
parent 0e1fb7afcc
commit c6f9261711
4 changed files with 63 additions and 22 deletions
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4
test/CodeGen/ARM/str_pre-2.ll
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@@ -4,8 +4,8 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
; CHECK: push {lr}
; CHECK: ldmia sp!, {pc}
; CHECK: str lr, [sp, #-4]!
; CHECK: ldr lr, [sp], #4
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a