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Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
e1a2587ee2
commit
c7139a6f0d
@ -161,6 +161,8 @@ namespace {
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// are already handled elsewhere. They are placeholders to allow this
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// encoder to continue to function until the MC encoder is sufficiently
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// far along that this one can be eliminated entirely.
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unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
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const { return 0; }
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
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@ -1868,6 +1868,7 @@ class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
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: NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
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pattern> {
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let Inst{31-25} = 0b1111001;
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string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
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}
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class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
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@ -172,6 +172,9 @@ public:
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unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const;
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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@ -195,6 +198,26 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
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return new ARMMCCodeEmitter(TM, Ctx);
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}
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/// NEONThumb2PostEncoder - Post-process encoded NEON data-processing
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/// instructions, and rewrite them to their Thumb2 form if we are currently in
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/// Thumb2 mode.
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unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
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unsigned EncodedValue) const {
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb2()) {
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// NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
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// to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
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// set to 1111.
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unsigned Bit24 = EncodedValue & 0x01000000;
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unsigned Bit28 = Bit24 << 4;
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EncodedValue &= 0xEFFFFFFF;
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EncodedValue |= Bit28;
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EncodedValue |= 0x0F000000;
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}
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return EncodedValue;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned ARMMCCodeEmitter::
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33
test/MC/ARM/neont2-abs-encoding.s
Normal file
33
test/MC/ARM/neont2-abs-encoding.s
Normal file
@ -0,0 +1,33 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
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.code 16
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@ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xff]
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vabs.s8 d16, d16
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@ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xff]
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vabs.s16 d16, d16
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@ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xff]
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vabs.s32 d16, d16
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@ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xff]
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vabs.f32 d16, d16
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@ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xff]
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vabs.s8 q8, q8
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@ CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xff]
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vabs.s16 q8, q8
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@ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xff]
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vabs.s32 q8, q8
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@ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xff]
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vabs.f32 q8, q8
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@ CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xff]
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vqabs.s8 d16, d16
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@ CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xff]
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vqabs.s16 d16, d16
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@ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xff]
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vqabs.s32 d16, d16
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@ CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xff]
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vqabs.s8 q8, q8
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@ CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xff]
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vqabs.s16 q8, q8
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@ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xff]
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vqabs.s32 q8, q8
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138
test/MC/ARM/neont2-add-encoding.s
Normal file
138
test/MC/ARM/neont2-add-encoding.s
Normal file
@ -0,0 +1,138 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
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.code 16
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@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xef]
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vadd.i8 d16, d17, d16
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@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xef]
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vadd.i16 d16, d17, d16
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@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xef]
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vadd.i64 d16, d17, d16
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@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xef]
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vadd.i32 d16, d17, d16
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@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xef]
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vadd.f32 d16, d16, d17
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@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xef]
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vadd.f32 q8, q8, q9
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@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xef]
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vaddl.s8 q8, d17, d16
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@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xef]
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vaddl.s16 q8, d17, d16
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@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xef]
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vaddl.s32 q8, d17, d16
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@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xff]
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vaddl.u8 q8, d17, d16
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@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xff]
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vaddl.u16 q8, d17, d16
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@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xff]
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vaddl.u32 q8, d17, d16
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@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xef]
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vaddw.s8 q8, q8, d18
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@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xef]
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vaddw.s16 q8, q8, d18
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@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xef]
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vaddw.s32 q8, q8, d18
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@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xff]
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vaddw.u8 q8, q8, d18
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@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xff]
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vaddw.u16 q8, q8, d18
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@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xff]
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vaddw.u32 q8, q8, d18
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@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xef]
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vhadd.s8 d16, d16, d17
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@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xef]
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vhadd.s16 d16, d16, d17
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@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xef]
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vhadd.s32 d16, d16, d17
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@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xff]
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vhadd.u8 d16, d16, d17
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@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xff]
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vhadd.u16 d16, d16, d17
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@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xff]
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vhadd.u32 d16, d16, d17
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@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xef]
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vhadd.s8 q8, q8, q9
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@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xef]
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vhadd.s16 q8, q8, q9
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@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xef]
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vhadd.s32 q8, q8, q9
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@ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xff]
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vhadd.u8 q8, q8, q9
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@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xff]
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vhadd.u16 q8, q8, q9
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@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xff]
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vhadd.u32 q8, q8, q9
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@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xef]
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vrhadd.s8 d16, d16, d17
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@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xef]
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vrhadd.s16 d16, d16, d17
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@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xef]
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vrhadd.s32 d16, d16, d17
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@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xff]
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vrhadd.u8 d16, d16, d17
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@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xff]
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vrhadd.u16 d16, d16, d17
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@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xff]
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vrhadd.u32 d16, d16, d17
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@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xef]
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vrhadd.s8 q8, q8, q9
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@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xef]
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vrhadd.s16 q8, q8, q9
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@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xef]
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vrhadd.s32 q8, q8, q9
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@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xff]
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vrhadd.u8 q8, q8, q9
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@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xff]
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vrhadd.u16 q8, q8, q9
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@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xff]
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vrhadd.u32 q8, q8, q9
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@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xef]
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vqadd.s8 d16, d16, d17
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@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xef]
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vqadd.s16 d16, d16, d17
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@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xef]
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vqadd.s32 d16, d16, d17
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@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xef]
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vqadd.s64 d16, d16, d17
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@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xff]
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vqadd.u8 d16, d16, d17
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@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xff]
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vqadd.u16 d16, d16, d17
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@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xff]
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vqadd.u32 d16, d16, d17
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@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xff]
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vqadd.u64 d16, d16, d17
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@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xef]
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vqadd.s8 q8, q8, q9
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@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xef]
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vqadd.s16 q8, q8, q9
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@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xef]
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vqadd.s32 q8, q8, q9
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@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xef]
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vqadd.s64 q8, q8, q9
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@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xff]
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vqadd.u8 q8, q8, q9
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@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xff]
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vqadd.u16 q8, q8, q9
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@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xff]
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vqadd.u32 q8, q8, q9
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@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xff]
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vqadd.u64 q8, q8, q9
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@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xef]
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vaddhn.i16 d16, q8, q9
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@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xef]
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vaddhn.i32 d16, q8, q9
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@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xef]
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vaddhn.i64 d16, q8, q9
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@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xff]
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vraddhn.i16 d16, q8, q9
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@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xff]
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vraddhn.i32 d16, q8, q9
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@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xff]
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vraddhn.i64 d16, q8, q9
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