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[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-08-23 10:10:13 +00:00
parent bbe88b7f0d
commit c73488a38e
4 changed files with 482 additions and 477 deletions
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926
lib/Target/Mips/MipsMSAInstrInfo.td
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File diff suppressed because it is too large Load Diff

11
lib/Target/Mips/MipsRegisterInfo.td
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@ -318,9 +318,14 @@ def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
Unallocatable;
def MSA128: RegisterClass<"Mips",
[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],
128, (sequence "W%u", 0, 31)>;
def MSA128B: RegisterClass<"Mips", [v16i8], 128,
(sequence "W%u", 0, 31)>;
def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
(sequence "W%u", 0, 31)>;
def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
(sequence "W%u", 0, 31)>;
def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
(sequence "W%u", 0, 31)>;
// Hi/Lo Registers
def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;

20
lib/Target/Mips/MipsSEISelLowering.cpp
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@ -78,13 +78,13 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::MUL, MVT::v2i16, Legal);
if (Subtarget->hasMSA()) {
addMSAType(MVT::v16i8);
addMSAType(MVT::v8i16);
addMSAType(MVT::v4i32);
addMSAType(MVT::v2i64);
addMSAType(MVT::v8f16);
addMSAType(MVT::v4f32);
addMSAType(MVT::v2f64);
addMSAType(MVT::v16i8, &Mips::MSA128BRegClass);
addMSAType(MVT::v8i16, &Mips::MSA128HRegClass);
addMSAType(MVT::v4i32, &Mips::MSA128WRegClass);
addMSAType(MVT::v2i64, &Mips::MSA128DRegClass);
addMSAType(MVT::v8f16, &Mips::MSA128HRegClass);
addMSAType(MVT::v4f32, &Mips::MSA128WRegClass);
addMSAType(MVT::v2f64, &Mips::MSA128DRegClass);
}
if (!TM.Options.UseSoftFloat) {
@ -133,9 +133,9 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
return new MipsSETargetLowering(TM);
}
void
MipsSETargetLowering::addMSAType(MVT::SimpleValueType Ty) {
addRegisterClass(Ty, &Mips::MSA128RegClass);
void MipsSETargetLowering::
addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
addRegisterClass(Ty, RC);
// Expand all builtin opcodes.
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)

2
lib/Target/Mips/MipsSEISelLowering.h
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@ -22,7 +22,7 @@ namespace llvm {
public:
explicit MipsSETargetLowering(MipsTargetMachine &TM);
void addMSAType(MVT::SimpleValueType Ty);
void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;