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Moved code to modify the opcode from 'reg' to 'imm' form to a more logical place.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-06-03 03:18:20 +00:00
parent 534538921d
commit c740aae220
2 changed files with 12 additions and 30 deletions
lib
CodeGen/InstrSelection
InstrSelectionSupport.cpp
Target/SparcV9/InstrSelection
InstrSelectionSupport.cpp

21
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp

@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
else {
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
}
else
@ -219,21 +213,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
: (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
}
else
{
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
if (opType == MachineOperand::MO_MachineRegister)
minstr->SetMachineOperandReg(op, machineRegNum);
else if (opType == MachineOperand::MO_SignExtendedImmed ||
opType == MachineOperand::MO_UnextendedImmed)
opType == MachineOperand::MO_UnextendedImmed) {
minstr->SetMachineOperandConst(op, opType, immedValue);
else if (constantThatMustBeLoaded ||
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
} else if (constantThatMustBeLoaded ||
(opValue && isa<GlobalValue>(opValue)))
{ // opValue is a constant that must be explicitly loaded into a reg
assert(opValue);

21
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp

@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
else {
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
}
else
@ -219,21 +213,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
: (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
}
else
{
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
if (opType == MachineOperand::MO_MachineRegister)
minstr->SetMachineOperandReg(op, machineRegNum);
else if (opType == MachineOperand::MO_SignExtendedImmed ||
opType == MachineOperand::MO_UnextendedImmed)
opType == MachineOperand::MO_UnextendedImmed) {
minstr->SetMachineOperandConst(op, opType, immedValue);
else if (constantThatMustBeLoaded ||
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
} else if (constantThatMustBeLoaded ||
(opValue && isa<GlobalValue>(opValue)))
{ // opValue is a constant that must be explicitly loaded into a reg
assert(opValue);