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80 col violation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-25 01:55:25 +00:00
parent fd87a544c0
commit c7423aff68
1 changed files with 2 additions and 1 deletions
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3
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -959,7 +959,8 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
// Build the new ADD / SUB.
BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
unsigned Opc = TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri);
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
.addReg(BaseReg, RegState::Kill).addImm(ThisVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;