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Add instruction patterns and encodings for the x86 bt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61400 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6513,6 +6513,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CALL: return "X86ISD::CALL";
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case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::BT: return "X86ISD::BT";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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@ -115,6 +115,9 @@ namespace llvm {
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 bit-test instructions.
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BT,
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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@ -917,6 +917,20 @@ def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
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(implicit EFLAGS)]>;
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} // Defs = [EFLAGS]
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// Bit tests.
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// TODO: BT with immediate operands.
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// TODO: BTC, BTR, and BTS
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let Defs = [EFLAGS] in {
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def BT64rr : RI<0xA3, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
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"bt{q}\t{$src2, $src1|$src1, $src2}",
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[(X86bt GR64:$src1, GR64:$src2),
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(implicit EFLAGS)]>;
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def BT64mr : RI<0xA3, MRMSrcMem, (outs), (ins i64mem:$src1, GR64:$src2),
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"bt{q}\t{$src2, $src1|$src1, $src2}",
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[(X86bt addr:$src1, GR64:$src2),
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(implicit EFLAGS)]>;
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} // Defs = [EFLAGS]
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// Conditional moves
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let Uses = [EFLAGS], isTwoAddress = 1 in {
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let isCommutable = 1 in {
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@ -76,6 +76,8 @@ def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
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def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
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def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
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def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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[SDNPHasChain]>;
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@ -2649,6 +2651,28 @@ def CMP32ri8 : Ii8<0x83, MRM7r,
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(implicit EFLAGS)]>;
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} // Defs = [EFLAGS]
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// Bit tests.
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// TODO: BT with immediate operands
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// TODO: BTC, BTR, and BTS
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let Defs = [EFLAGS] in {
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def BT16rr : I<0xA3, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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[(X86bt GR16:$src1, GR16:$src2),
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(implicit EFLAGS)]>, OpSize;
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def BT32rr : I<0xA3, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
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"bt{l}\t{$src2, $src1|$src1, $src2}",
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[(X86bt GR32:$src1, GR32:$src2),
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(implicit EFLAGS)]>;
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def BT16mr : I<0xA3, MRMSrcMem, (outs), (ins i16mem:$src1, GR16:$src2),
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"bt{w}\t{$src2, $src1|$src1, $src2}",
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[(X86bt addr:$src1, GR16:$src2),
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(implicit EFLAGS)]>, OpSize;
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def BT32mr : I<0xA3, MRMSrcMem, (outs), (ins i32mem:$src1, GR32:$src2),
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"bt{l}\t{$src2, $src1|$src1, $src2}",
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[(X86bt addr:$src1, GR32:$src2),
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(implicit EFLAGS)]>;
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} // Defs = [EFLAGS]
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// Sign/Zero extenders
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// Use movsbl intead of movsbw; we don't care about the high 16 bits
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// of the register here. This has a smaller encoding and avoids a
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