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Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a

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case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2010-04-16 22:40:20 +00:00
parent 003d7c4b5d
commit c7b65914e0
4 changed files with 29 additions and 5 deletions
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3
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -2104,7 +2104,7 @@ static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
case ESize64: {
for (unsigned i = 0; i < 8; ++i)
if ((Imm8 >> i) & 1)
Imm64 |= 0xFF << 8*i;
Imm64 |= 0xFFul << 8*i;
break;
}
default:
@ -2450,6 +2450,7 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
case ARM::VMOVv1i64:
case ARM::VMOVv2i64:
esize = ESize64;
break;
default:
assert(0 && "Unreachable code!");
return false;