From c7c44fa75eb63aab59fcd0a1dfd6522e21babf22 Mon Sep 17 00:00:00 2001
From: Elena Demikhovsky <elena.demikhovsky@intel.com>
Date: Sun, 10 May 2015 14:23:52 +0000
Subject: [PATCH] AVX-512: fixed UINT_TO_FP operation for 512-bit types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236955 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp |  7 +++++++
 test/CodeGen/X86/avx512-cvt.ll     | 17 +++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 557664c09dc..758ba3ab128 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1301,6 +1301,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     setOperationAction(ISD::UINT_TO_FP,         MVT::v16i32, Legal);
     setOperationAction(ISD::UINT_TO_FP,         MVT::v8i32, Legal);
     setOperationAction(ISD::UINT_TO_FP,         MVT::v4i32, Legal);
+    setOperationAction(ISD::UINT_TO_FP,         MVT::v16i8, Custom);
+    setOperationAction(ISD::UINT_TO_FP,         MVT::v16i16, Custom);
     setOperationAction(ISD::FP_ROUND,           MVT::v8f32, Legal);
     setOperationAction(ISD::FP_EXTEND,          MVT::v8f32, Legal);
 
@@ -11793,6 +11795,11 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
   case MVT::v4i32:
   case MVT::v8i32:
     return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
+  case MVT::v16i8:
+  case MVT::v16i16:
+    if (Subtarget->hasAVX512())
+      return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
+                         DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
   }
   llvm_unreachable(nullptr);
 }
diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll
index 842b9f8494b..a211bcd38c9 100644
--- a/test/CodeGen/X86/avx512-cvt.ll
+++ b/test/CodeGen/X86/avx512-cvt.ll
@@ -308,3 +308,20 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) {
   %1 = sitofp <8 x i1> %cmpres to <8 x double>
   ret <8 x double> %1
 }
+
+; CHECK-LABEL: @uitofp_16i8
+; CHECK:  vpmovzxbd  
+; CHECK: vcvtudq2ps
+define <16 x float> @uitofp_16i8(<16 x i8>%a) {
+  %b = uitofp <16 x i8> %a to <16 x float>
+  ret <16 x float>%b
+}
+
+; CHECK-LABEL: @uitofp_16i16
+; CHECK: vpmovzxwd
+; CHECK: vcvtudq2ps
+define <16 x float> @uitofp_16i16(<16 x i16>%a) {
+  %b = uitofp <16 x i16> %a to <16 x float>
+  ret <16 x float>%b
+}
+