mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6367cfc470
commit
c7d4655b57
@ -156,11 +156,11 @@ def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
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//===----------------------------------------------------------------------===//
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// Two address Instructions.
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//
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let Constraints = "$src1 = $dst" in {
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// unary instructions
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let CodeSize = 2 in {
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
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"neg{b}\t$dst",
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[(set GR8:$dst, (ineg GR8:$src1)),
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@ -173,8 +173,8 @@ def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
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"neg{l}\t$dst",
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[(set GR32:$dst, (ineg GR32:$src1)),
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(implicit EFLAGS)]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
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"neg{b}\t$dst",
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[(store (ineg (loadi8 addr:$dst)), addr:$dst),
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@ -187,9 +187,12 @@ let Constraints = "" in {
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"neg{l}\t$dst",
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[(store (ineg (loadi32 addr:$dst)), addr:$dst),
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(implicit EFLAGS)]>;
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} // Constraints = ""
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} // Defs = [EFLAGS]
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// FIXME: NOT sets EFLAGS!
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let Constraints = "$src1 = $dst" in {
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// Match xor -1 to not. Favors these over a move imm + xor to save code size.
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let AddedComplexity = 15 in {
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def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
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@ -202,7 +205,8 @@ def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
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"not{l}\t$dst",
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[(set GR32:$dst, (not GR32:$src1))]>;
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}
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let Constraints = "" in {
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} // Constraints = "$src1 = $dst"
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def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
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"not{b}\t$dst",
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[(store (not (loadi8 addr:$dst)), addr:$dst)]>;
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@ -212,11 +216,11 @@ let Constraints = "" in {
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def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
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"not{l}\t$dst",
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[(store (not (loadi32 addr:$dst)), addr:$dst)]>;
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} // Constraints = ""
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} // CodeSize
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// TODO: inc/dec is slow for P4, but fast for Pentium-M.
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let CodeSize = 2 in
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def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
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"inc{b}\t$dst",
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@ -232,7 +236,9 @@ def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
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Requires<[In32BitMode]>;
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}
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let Constraints = "", CodeSize = 2 in {
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} // Constraints = "$src1 = $dst"
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let CodeSize = 2 in {
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def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
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[(store (add (loadi8 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)]>;
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@ -244,8 +250,9 @@ let Constraints = "", CodeSize = 2 in {
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[(store (add (loadi32 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)]>,
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Requires<[In32BitMode]>;
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} // Constraints = "", CodeSize = 2
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} // CodeSize = 2
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let Constraints = "$src1 = $dst" in {
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let CodeSize = 2 in
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def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
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"dec{b}\t$dst",
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@ -260,8 +267,10 @@ def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
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Requires<[In32BitMode]>;
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} // CodeSize = 2
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} // Constraints = "$src1 = $dst"
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let Constraints = "", CodeSize = 2 in {
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let CodeSize = 2 in {
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def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
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[(store (add (loadi8 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)]>;
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@ -273,11 +282,12 @@ let Constraints = "", CodeSize = 2 in {
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[(store (add (loadi32 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)]>,
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Requires<[In32BitMode]>;
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} // Constraints = "", CodeSize = 2
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} // CodeSize = 2
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} // Defs = [EFLAGS]
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// Logical operators...
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// Logical operators.
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
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def AND8rr : I<0x20, MRMDestReg,
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(outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
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@ -293,7 +303,8 @@ def AND32rr : I<0x21, MRMDestReg,
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"and{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
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GR32:$src2))]>;
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}
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} // isCommutable
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// AND instructions with the destination register in REG and the source register
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// in R/M. Included for the disassembler.
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@ -351,8 +362,8 @@ def AND32ri8 : Ii8<0x83, MRM4r,
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"and{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
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i32immSExt8:$src2))]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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def AND8mr : I<0x20, MRMDestMem,
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(outs), (ins i8mem :$dst, GR8 :$src),
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"and{b}\t{$src, $dst|$dst, $src}",
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@ -397,6 +408,7 @@ let Constraints = "" in {
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[(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
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(implicit EFLAGS)]>;
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// FIXME: Implicitly modifiers AL.
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def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
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"and{b}\t{$src, %al|%al, $src}", []>;
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def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
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@ -404,8 +416,7 @@ let Constraints = "" in {
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def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
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"and{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
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def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
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@ -478,7 +489,8 @@ def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
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"or{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
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i32immSExt8:$src2))]>;
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let Constraints = "" in {
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} // Constraints = "$src1 = $dst"
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def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
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"or{b}\t{$src, $dst|$dst, $src}",
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[(store (or (load addr:$dst), GR8:$src), addr:$dst),
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@ -520,9 +532,10 @@ let Constraints = "" in {
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"or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
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"or{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
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def XOR8rr : I<0x30, MRMDestReg,
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(outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
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@ -596,8 +609,9 @@ def XOR32ri8 : Ii8<0x83, MRM6r,
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"xor{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
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i32immSExt8:$src2))]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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def XOR8mr : I<0x30, MRMDestMem,
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(outs), (ins i8mem :$dst, GR8 :$src),
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"xor{b}\t{$src, $dst|$dst, $src}",
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@ -648,12 +662,12 @@ let Constraints = "" in {
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"xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
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"xor{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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} // Defs = [EFLAGS]
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// Arithmetic.
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
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// Register-Register Addition
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def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
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@ -733,8 +747,8 @@ def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
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[(set GR32:$dst, EFLAGS,
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(X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
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}
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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// Memory-Register Addition
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def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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@ -778,9 +792,9 @@ let Constraints = "" in {
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"add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
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"add{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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let Uses = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
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def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"adc{b}\t{$src2, $dst|$dst, $src2}",
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@ -839,8 +853,8 @@ def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
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(ins GR32:$src1, i32i8imm:$src2),
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"adc{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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"adc{b}\t{$src2, $dst|$dst, $src2}",
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[(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
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@ -875,9 +889,10 @@ let Constraints = "" in {
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"adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
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"adc{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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} // Uses = [EFLAGS]
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let Constraints = "$src1 = $dst" in {
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// Register-Register Subtraction
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def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"sub{b}\t{$src2, $dst|$dst, $src2}",
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@ -946,8 +961,8 @@ def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
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"sub{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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// Memory-Register Subtraction
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def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
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"sub{b}\t{$src2, $dst|$dst, $src2}",
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@ -992,9 +1007,9 @@ let Constraints = "" in {
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"sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
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"sub{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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let Uses = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
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(ins GR8:$src1, GR8:$src2),
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"sbb{b}\t{$src2, $dst|$dst, $src2}",
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@ -1007,8 +1022,9 @@ def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
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(ins GR32:$src1, GR32:$src2),
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"sbb{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
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} // Constraints = "$src1 = $dst"
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let Constraints = "" in {
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def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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"sbb{b}\t{$src2, $dst|$dst, $src2}",
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[(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
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@ -1043,7 +1059,8 @@ let Constraints = "" in {
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"sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
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"sbb{l}\t{$src, %eax|%eax, $src}", []>;
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} // Constraints = ""
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let Constraints = "$src1 = $dst" in {
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let isCodeGenOnly = 1 in {
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def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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@ -1088,10 +1105,14 @@ def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
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(ins GR32:$src1, i32i8imm:$src2),
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"sbb{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
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} // Constraints = "$src1 = $dst"
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} // Uses = [EFLAGS]
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} // Defs = [EFLAGS]
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
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// Register-Register Signed Integer Multiply
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def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
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@ -1116,8 +1137,9 @@ def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
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} // Constraints = "$src1 = $dst"
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} // Defs = [EFLAGS]
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} // end Two Address instructions
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// Suprisingly enough, these are not two address instructions!
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let Defs = [EFLAGS] in {
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