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Fix VirtRegMap to use TRI::index2VirtReg and TRI::virtReg2Index instead of

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depending on TRI::FirstVirtualRegister.

Also use TRI::printReg instead of printing virtual registers directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-01-08 23:11:07 +00:00
parent 98c5476070
commit c7d67f90d3
3 changed files with 34 additions and 20 deletions
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8
include/llvm/Target/TargetRegisterInfo.h
View File

@ -321,6 +321,12 @@ public:
return Reg >= FirstVirtualRegister;
}
/// virtReg2Index - Convert a virtual register number to a 0-based index.
/// The first virtual register in a function will get the index 0.
static unsigned virtReg2Index(unsigned Reg) {
return Reg - FirstVirtualRegister;
}
/// index2VirtReg - Convert a 0-based index to a virtual register number.
/// This is the inverse operation of VirtReg2IndexFunctor below.
static unsigned index2VirtReg(unsigned Index) {
@ -743,7 +749,7 @@ public:
// This is useful when building IndexedMaps keyed on virtual registers
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
unsigned operator()(unsigned Reg) const {
return Reg - TargetRegisterInfo::FirstVirtualRegister;
return TargetRegisterInfo::virtReg2Index(Reg);
}
};

42
lib/CodeGen/VirtRegMap.cpp
View File

@ -74,8 +74,7 @@ bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
EmergencySpillSlots.clear();
SpillSlotToUsesMap.resize(8);
ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
TargetRegisterInfo::FirstVirtualRegister);
ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
allocatableRCRegs.clear();
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
@ -96,7 +95,7 @@ void VirtRegMap::grow() {
Virt2SplitMap.grow(LastVirtReg);
Virt2SplitKillMap.grow(LastVirtReg);
ReMatMap.grow(LastVirtReg);
ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
}
unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
@ -229,10 +228,11 @@ bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
UnusedRegs.resize(NumRegs);
BitVector Used(NumRegs);
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
Used.set(Virt2PhysMap[i]);
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
Used.set(Virt2PhysMap[Reg]);
}
BitVector Allocatable = TRI->getAllocatableSet(*MF);
bool AnyUnused = false;
@ -260,18 +260,26 @@ void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
const MachineRegisterInfo &MRI = MF->getRegInfo();
OS << "********** REGISTER MAP **********\n";
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
<< "] " << MRI.getRegClass(i)->getName() << "\n";
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
OS << '[';
TRI->printReg(Reg, OS);
OS << " -> ";
TRI->printReg(Virt2PhysMap[Reg], OS);
OS << "] " << MRI.getRegClass(i)->getName() << "\n";
}
}
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i]
<< "] " << MRI.getRegClass(i)->getName() << "\n";
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
OS << '[';
TRI->printReg(Reg, OS);
OS << " -> fi#" << Virt2StackSlotMap[Reg]
<< "] " << MRI.getRegClass(Reg)->getName() << "\n";
}
}
OS << '\n';
}

4
lib/CodeGen/VirtRegMap.h
View File

@ -432,12 +432,12 @@ namespace llvm {
/// @brief Mark the specified register as being implicitly defined.
void setIsImplicitlyDefined(unsigned VirtReg) {
ImplicitDefed.set(VirtReg-TargetRegisterInfo::FirstVirtualRegister);
ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg));
}
/// @brief Returns true if the virtual register is implicitly defined.
bool isImplicitlyDefined(unsigned VirtReg) const {
return ImplicitDefed[VirtReg-TargetRegisterInfo::FirstVirtualRegister];
return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)];
}
/// @brief Updates information about the specified virtual register's value