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In FastISel mode, the scheduler may be invoked multiple times
in the same block. Fix the entry-block handling to only run at at the beginning of the entry block, and not any other times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55817 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -731,7 +731,9 @@ void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
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/// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAG::EmitSchedule() {
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bool isEntryBB = &MF->front() == BB;
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// If we're emitting the first code into the entry block, we
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// have additional work to do.
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bool isEntryBB = &MF->front() == BB && BB->empty();
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if (isEntryBB && !SchedLiveInCopies) {
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// If this is the first basic block in the function, and if it has live ins
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