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In FastISel mode, the scheduler may be invoked multiple times

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in the same block. Fix the entry-block handling to only run at
at the beginning of the entry block, and not any other times.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55817 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-05 01:07:48 +00:00
parent d89ae99ec8
commit c7f4a8a80c
1 changed files with 3 additions and 1 deletions
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4
lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
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@ -731,7 +731,9 @@ void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
/// EmitSchedule - Emit the machine code in scheduled order.
MachineBasicBlock *ScheduleDAG::EmitSchedule() {
bool isEntryBB = &MF->front() == BB;
// If we're emitting the first code into the entry block, we
// have additional work to do.
bool isEntryBB = &MF->front() == BB && BB->empty();
if (isEntryBB && !SchedLiveInCopies) {
// If this is the first basic block in the function, and if it has live ins