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Add intrinsics for the zext / sext instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-07-19 13:28:50 +00:00
parent 829bef1a46
commit c8007ab582
3 changed files with 47 additions and 7 deletions
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4
include/llvm/IntrinsicsXCore.td
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@ -17,6 +17,10 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
def int_xcore_crc32 : Intrinsic<[llvm_i32_ty], def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;

16
lib/Target/XCore/XCoreInstrInfo.td
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@ -754,7 +754,7 @@ def BL_lu10 : _FLU10<
} }
// Two operand short // Two operand short
// TODO eet, eef, tsetmr, sext (reg), zext (reg) // TODO eet, eef, tsetmr
def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
"not $dst, $b", "not $dst, $b",
[(set GRRegs:$dst, (not GRRegs:$b))]>; [(set GRRegs:$dst, (not GRRegs:$b))]>;
@ -764,15 +764,21 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
[(set GRRegs:$dst, (ineg GRRegs:$b))]>; [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
let neverHasSideEffects = 1 in
def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"sext $dst, $src2", "sext $dst, $src2",
[]>; [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>;
def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
let neverHasSideEffects = 1 in
def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"zext $dst, $src2", "zext $dst, $src2",
[]>; [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>;
def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"andnot $dst, $src2", "andnot $dst, $src2",

30
test/CodeGen/XCore/misc-intrinsics.ll
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@ -4,6 +4,8 @@
declare i32 @llvm.xcore.bitrev(i32) declare i32 @llvm.xcore.bitrev(i32)
declare i32 @llvm.xcore.crc32(i32, i32, i32) declare i32 @llvm.xcore.crc32(i32, i32, i32)
declare %0 @llvm.xcore.crc8(i32, i32, i32) declare %0 @llvm.xcore.crc8(i32, i32, i32)
declare i32 @llvm.xcore.zext(i32, i32)
declare i32 @llvm.xcore.sext(i32, i32)
define i32 @bitrev(i32 %val) { define i32 @bitrev(i32 %val) {
; CHECK: bitrev: ; CHECK: bitrev:
@ -25,3 +27,31 @@ define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
ret %0 %result ret %0 %result
} }
define i32 @zext(i32 %a, i32 %b) {
; CHECK: zext:
; CHECK: zext r0, r1
%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
ret i32 %result
}
define i32 @zexti(i32 %a) {
; CHECK: zexti:
; CHECK: zext r0, 4
%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
ret i32 %result
}
define i32 @sext(i32 %a, i32 %b) {
; CHECK: sext:
; CHECK: sext r0, r1
%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
ret i32 %result
}
define i32 @sexti(i32 %a) {
; CHECK: sexti:
; CHECK: sext r0, 4
%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
ret i32 %result
}