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Use instruction itinerary to determine what instructions are 'cheap'.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-10-26 02:08:50 +00:00
parent 0e9996ca94
commit c8141dfc7f
5 changed files with 69 additions and 4 deletions
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lib/CodeGen/MachineLICM.cpp
+36 -4
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@@ -173,7 +173,10 @@ namespace {
/// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
/// and an use in the current loop, return true if the target considered
/// it 'high'.
bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg);
bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
unsigned Reg) const;
bool IsCheapInstruction(MachineInstr &MI) const;
/// CanCauseHighRegPressure - Visit BBs from header to current BB,
/// check if hoisting an instruction of the given cost matrix can cause high
@@ -795,13 +798,15 @@ bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
/// and an use in the current loop, return true if the target considered
/// it 'high'.
bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
unsigned DefIdx, unsigned Reg) {
if (MRI->use_nodbg_empty(Reg))
unsigned DefIdx, unsigned Reg) const {
if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
return false;
for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
E = MRI->use_nodbg_end(); I != E; ++I) {
MachineInstr *UseMI = &*I;
if (UseMI->isCopyLike())
continue;
if (!CurLoop->contains(UseMI->getParent()))
continue;
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
@@ -823,6 +828,33 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
return false;
}
/// IsCheapInstruction - Return true if the instruction is marked "cheap" or
/// the operand latency between its def and a use is one or less.
bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
return true;
if (!InstrItins || InstrItins->isEmpty())
return false;
bool isCheap = false;
unsigned NumDefs = MI.getDesc().getNumDefs();
for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
MachineOperand &DefMO = MI.getOperand(i);
if (!DefMO.isReg() || !DefMO.isDef())
continue;
--NumDefs;
unsigned Reg = DefMO.getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
if (!TII->hasLowDefLatency(InstrItins, &MI, i))
return false;
isCheap = true;
}
return isCheap;
}
/// CanCauseHighRegPressure - Visit BBs from header to current BB, check
/// if hoisting an instruction of the given cost matrix can cause high
/// register pressure.
@@ -905,7 +937,7 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
// trade off is it may cause spill in high pressure situation. It will end up
// adding a store in the loop preheader. But the reload is no more expensive.
// The side benefit is these loads are frequently CSE'ed.
if (MI.getDesc().isAsCheapAsAMove()) {
if (IsCheapInstruction(MI)) {
if (!TII->isTriviallyReMaterializable(&MI, AA))
return false;
} else {