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eliminate more redundant constraint type analysis

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-04-28 21:03:16 +00:00
parent 2a600be226
commit c83994e5d4
1 changed files with 2 additions and 6 deletions
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8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -3320,12 +3320,8 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
switch (OpInfo.Type) {
case InlineAsm::isOutput: {
TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
if (CTy != TargetLowering::C_RegisterClass &&
CTy != TargetLowering::C_Register) {
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
OpInfo.ConstraintType != TargetLowering::C_Register) {
// Memory output, or 'other' output (e.g. 'X' constraint).
SDOperand InOperandVal = OpInfo.CallOperand;