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https://github.com/c64scene-ar/llvm-6502.git
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[C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -248,9 +248,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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}
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// These libcalls are not available in 32-bit.
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setLibcallName(RTLIB::SHL_I128, 0);
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setLibcallName(RTLIB::SRL_I128, 0);
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setLibcallName(RTLIB::SRA_I128, 0);
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setLibcallName(RTLIB::SHL_I128, nullptr);
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setLibcallName(RTLIB::SRL_I128, nullptr);
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setLibcallName(RTLIB::SRA_I128, nullptr);
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if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
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!Subtarget->isTargetWindows()) {
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@@ -915,7 +915,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// and extractions.
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std::pair<const TargetRegisterClass*, uint8_t>
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ARMTargetLowering::findRepresentativeClass(MVT VT) const{
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const TargetRegisterClass *RRC = 0;
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const TargetRegisterClass *RRC = nullptr;
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uint8_t Cost = 1;
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switch (VT.SimpleTy) {
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default:
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@@ -952,7 +952,7 @@ ARMTargetLowering::findRepresentativeClass(MVT VT) const{
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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default: return nullptr;
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case ARMISD::Wrapper: return "ARMISD::Wrapper";
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case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
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case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
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@@ -1359,7 +1359,7 @@ void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
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RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
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else {
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assert(NextVA.isMemLoc());
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if (StackPtr.getNode() == 0)
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if (!StackPtr.getNode())
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StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
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MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
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@@ -2839,8 +2839,9 @@ ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
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// If there is no regs to be stored, just point address after last
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// argument passed via stack.
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int FrameIndex =
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StoreByValRegs(CCInfo, DAG, dl, Chain, 0, CCInfo.getInRegsParamsCount(),
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0, ArgOffset, 0, ForceMutable, 0, TotalArgRegsSaveSize);
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StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
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CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
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0, TotalArgRegsSaveSize);
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AFI->setVarArgsFrameIndex(FrameIndex);
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}
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@@ -6760,8 +6761,8 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned UnitSize = 0;
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const TargetRegisterClass *TRC = 0;
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const TargetRegisterClass *VecTRC = 0;
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const TargetRegisterClass *TRC = nullptr;
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const TargetRegisterClass *VecTRC = nullptr;
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bool IsThumb1 = Subtarget->isThumb1Only();
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bool IsThumb2 = Subtarget->isThumb2();
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@@ -6795,7 +6796,7 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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? (const TargetRegisterClass *)&ARM::DPairRegClass
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: UnitSize == 8
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? (const TargetRegisterClass *)&ARM::DPRRegClass
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: 0;
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: nullptr;
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unsigned BytesLeft = SizeVal % UnitSize;
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unsigned LoopSize = SizeVal - BytesLeft;
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@@ -7586,7 +7587,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
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// Look for the glued ADDE.
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SDNode* AddeNode = AddcNode->getGluedUser();
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if (AddeNode == NULL)
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if (!AddeNode)
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return SDValue();
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// Make sure it is really an ADDE.
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@@ -7621,9 +7622,9 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
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// Figure out the high and low input values to the MLAL node.
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SDValue* HiMul = &MULOp;
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SDValue* HiAdd = NULL;
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SDValue* LoMul = NULL;
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SDValue* LowAdd = NULL;
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SDValue* HiAdd = nullptr;
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SDValue* LoMul = nullptr;
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SDValue* LowAdd = nullptr;
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if (IsLeftOperandMUL)
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HiAdd = &AddeOp1;
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@@ -7640,7 +7641,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
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LowAdd = &AddcOp0;
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}
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if (LoMul == NULL)
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if (!LoMul)
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return SDValue();
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if (LoMul->getNode() != HiMul->getNode())
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@@ -10058,7 +10059,7 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
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Value *CallOperandVal = info.CallOperandVal;
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// If we don't have a value, we can't do a match,
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// but allow it at the lowest weight.
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if (CallOperandVal == NULL)
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if (!CallOperandVal)
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return CW_Default;
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Type *type = CallOperandVal->getType();
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// Look at the constraint type.
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@@ -10137,7 +10138,7 @@ void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue>&Ops,
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SelectionDAG &DAG) const {
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SDValue Result(0, 0);
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SDValue Result;
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// Currently only support length 1 constraints.
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if (Constraint.length() != 1) return;
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