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InstCombine: Don't unconditionally preserve 'nsw' when shrinking constants
Consider: %add = add nsw i32 %a, -16777216 %and = and i32 %add, 255 Regardless of whether or not we demand the sign bit of %add, we cannot replace -16777216 with 2130706432 without also removing 'nsw' from the instruction. This fixes PR20377. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216261 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -43,6 +43,14 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
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// This instruction is producing bits that are not demanded. Shrink the RHS.
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Demanded &= OpC->getValue();
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I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
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// If 'nsw' is set and the constant is negative, removing *any* bits from the
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// constant could make overflow occur. Remove 'nsw' from the instruction in
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// this case.
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if (auto *OBO = dyn_cast<OverflowingBinaryOperator>(I))
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if (OBO->hasNoSignedWrap() && OpC->getValue().isNegative())
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cast<BinaryOperator>(OBO)->setHasNoSignedWrap(false);
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return true;
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}
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@ -1022,7 +1022,19 @@ define i64 @test83(i16 %a, i64 %k) {
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ret i64 %sh_prom1
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; CHECK-LABEL: @test83(
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; CHECK: %sub = add nsw i64 %k, 4294967295
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; CHECK: %sub = add i64 %k, 4294967295
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; CHECK: %sh_prom = trunc i64 %sub to i32
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; CHECK: %shl = shl i32 %conv, %sh_prom
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}
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define i8 @test84(i32 %a) {
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%add = add nsw i32 %a, -16777216
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%shr = lshr exact i32 %add, 23
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%trunc = trunc i32 %shr to i8
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ret i8 %trunc
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; CHECK-LABEL: @test84(
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; CHECK: [[ADD:%.*]] = add i32 %a, 2130706432
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; CHECK: [[SHR:%.*]] = lshr exact i32 [[ADD]], 23
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; CHECK: [[CST:%.*]] = trunc i32 [[SHR]] to i8
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}
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