mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-07 12:28:24 +00:00
ptx: remove reg-reg addressing mode and st.const
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122653 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -67,8 +67,8 @@ bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
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isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
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return false;
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return false;
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R1 = Addr.getOperand(0);
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R1 = Addr;
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R2 = Addr.getOperand(1);
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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return true;
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}
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}
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@@ -76,17 +76,20 @@ bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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SDValue &Offset) {
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if (Addr.getOpcode() != ISD::ADD) {
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if (Addr.getOpcode() != ISD::ADD) {
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// let SelectADDRii handle the [imm] case
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if (isImm(Addr))
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if (isImm(Addr))
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return false;
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return false;
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// is [reg] but not [imm]
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// it is [reg]
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Base = Addr;
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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return true;
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}
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}
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if (Addr.getNumOperands() < 2)
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return false;
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// let SelectADDRii handle the [imm+imm] case
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// let SelectADDRii handle the [imm+imm] case
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if (Addr.getNumOperands() >= 2 &&
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if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
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isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
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return false;
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return false;
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// try [reg+imm] and [imm+reg]
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// try [reg+imm] and [imm+reg]
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@@ -96,13 +99,7 @@ bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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return true;
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return true;
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}
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}
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// either [reg+imm] and [imm+reg]
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// neither [reg+imm] nor [imm+reg]
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for (int i = 0; i < 2; i ++)
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if (SelectImm(Addr.getOperand(1-i), Offset)) {
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Base = Addr.getOperand(i);
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return true;
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}
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return false;
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return false;
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}
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}
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@@ -76,16 +76,6 @@ def store_global
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return false;
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return false;
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}]>;
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}]>;
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def store_constant
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::CONSTANT;
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return false;
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}]>;
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def store_local
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def store_local
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const Value *Src;
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@@ -122,10 +112,6 @@ def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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// Address operands
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// Address operands
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def MEMrr : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegs32, RRegs32);
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}
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def MEMri : Operand<i32> {
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def MEMri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegs32, i32imm);
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let MIOperandInfo = (ops RRegs32, i32imm);
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@@ -182,7 +168,7 @@ multiclass INT3ntnc<string opcstr, SDNode opnode> {
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multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
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multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
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def rr : InstPTX<(outs RC:$d),
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def rr : InstPTX<(outs RC:$d),
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(ins MEMrr:$a),
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(ins MEMri:$a),
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!strconcat(opstr, ".%type\t$d, [$a]"),
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!strconcat(opstr, ".%type\t$d, [$a]"),
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[(set RC:$d, (pat_load ADDRrr:$a))]>;
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[(set RC:$d, (pat_load ADDRrr:$a))]>;
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def ri : InstPTX<(outs RC:$d),
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def ri : InstPTX<(outs RC:$d),
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@@ -197,7 +183,7 @@ multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
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multiclass PTX_ST<string opstr, RegisterClass RC, PatFrag pat_store> {
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multiclass PTX_ST<string opstr, RegisterClass RC, PatFrag pat_store> {
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def rr : InstPTX<(outs),
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def rr : InstPTX<(outs),
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(ins RC:$d, MEMrr:$a),
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(ins RC:$d, MEMri:$a),
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!strconcat(opstr, ".%type\t[$a], $d"),
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!strconcat(opstr, ".%type\t[$a], $d"),
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[(pat_store RC:$d, ADDRrr:$a)]>;
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[(pat_store RC:$d, ADDRrr:$a)]>;
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def ri : InstPTX<(outs),
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def ri : InstPTX<(outs),
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@@ -251,7 +237,6 @@ defm LDp : PTX_LD<"ld.param", RRegs32, load_parameter>;
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defm LDs : PTX_LD<"ld.shared", RRegs32, load_shared>;
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defm LDs : PTX_LD<"ld.shared", RRegs32, load_shared>;
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defm STg : PTX_ST<"st.global", RRegs32, store_global>;
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defm STg : PTX_ST<"st.global", RRegs32, store_global>;
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defm STc : PTX_ST<"st.const", RRegs32, store_constant>;
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defm STl : PTX_ST<"st.local", RRegs32, store_local>;
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defm STl : PTX_ST<"st.local", RRegs32, store_local>;
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defm STp : PTX_ST<"st.param", RRegs32, store_parameter>;
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defm STp : PTX_ST<"st.param", RRegs32, store_parameter>;
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defm STs : PTX_ST<"st.shared", RRegs32, store_shared>;
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defm STs : PTX_ST<"st.shared", RRegs32, store_shared>;
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@@ -30,7 +30,8 @@ entry:
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define ptx_device i32 @t3(i32* %p, i32 %q) {
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define ptx_device i32 @t3(i32* %p, i32 %q) {
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entry:
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entry:
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;CHECK: shl.b32 r0, r2, 2;
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;CHECK: shl.b32 r0, r2, 2;
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;CHECK: ld.global.s32 r0, [r1+r0];
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;CHECK: add.s32 r0, r1, r0;
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;CHECK: ld.global.s32 r0, [r0];
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%i = getelementptr i32* %p, i32 %q
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%i = getelementptr i32* %p, i32 %q
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%x = load i32* %i
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%x = load i32* %i
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ret i32 %x
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ret i32 %x
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@@ -31,7 +31,8 @@ define ptx_device void @t3(i32* %p, i32 %q, i32 %x) {
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;CHECK: .reg .s32 r0;
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;CHECK: .reg .s32 r0;
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entry:
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entry:
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;CHECK: shl.b32 r0, r2, 2;
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;CHECK: shl.b32 r0, r2, 2;
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;CHECK: st.global.s32 [r1+r0], r3;
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;CHECK: add.s32 r0, r1, r0;
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;CHECK: st.global.s32 [r0], r3;
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%i = getelementptr i32* %p, i32 %q
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%i = getelementptr i32* %p, i32 %q
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store i32 %x, i32* %i
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store i32 %x, i32* %i
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ret void
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ret void
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@@ -45,14 +46,6 @@ entry:
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ret void
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ret void
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}
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}
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define ptx_device void @t4_const(i32 %x) {
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entry:
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;CHECK: st.const.s32 [array_constant], r1;
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%i = getelementptr [10 x i32] addrspace(1)* @array_constant, i32 0, i32 0
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store i32 %x, i32 addrspace(1)* %i
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ret void
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}
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define ptx_device void @t4_local(i32 %x) {
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define ptx_device void @t4_local(i32 %x) {
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entry:
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entry:
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;CHECK: st.local.s32 [array_local], r1;
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;CHECK: st.local.s32 [array_local], r1;
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