diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 659a7a2389e..11efdb78dce 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -288,7 +288,7 @@ defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
 // truncate
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
-      Requires<[IsN64, HasStdEnc]>;
+      Requires<[HasStdEnc]>;
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td
index ac40b118004..ed515ef0c96 100644
--- a/lib/Target/Mips/MipsCallingConv.td
+++ b/lib/Target/Mips/MipsCallingConv.td
@@ -27,7 +27,7 @@ def RetCC_MipsO32 : CallingConv<[
   CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
 
   // f64 are returned in register D0, D1
-  CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
+  CCIfType<[f64], CCAssignToReg<[D0, D1]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index 92a828c9f22..aef1ace461c 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -358,12 +358,12 @@ let Predicates = [HasStdEnc] in {
   def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>;
 }
 
-let Predicates = [HasMips64, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
   def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>;
   def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
 }
 
-let Predicates = [NotMips64, HasStdEnc] in {
+let Predicates = [NotFP64bit, HasStdEnc] in {
   let isPseudo = 1, isCodeGenOnly = 1 in {
     def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, load>;
     def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, store>;
@@ -600,12 +600,12 @@ let AddedComplexity = 40 in {
     def : StoreRegImmPat<SWC1, f32>;
   }
 
-  let Predicates = [HasMips64, HasStdEnc] in {
+  let Predicates = [IsFP64bit, HasStdEnc] in {
     def : LoadRegImmPat<LDC164, f64, load>;
     def : StoreRegImmPat<SDC164, f64>;
   }
 
-  let Predicates = [NotMips64, HasStdEnc] in {
+  let Predicates = [NotFP64bit, HasStdEnc] in {
     def : LoadRegImmPat<PseudoLDC1, f64, load>;
     def : StoreRegImmPat<PseudoSDC1, f64>;
   }