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The actual order of parameters in a 2-reg-immediate assembly instructions is

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"rs1, imm, rd": most importantly, rd goes last.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6456 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-05-31 04:22:26 +00:00
parent e236eca7bb
commit c89d256e95
1 changed files with 34 additions and 2 deletions
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36
lib/Target/SparcV9/SparcV9_F3.td
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@ -56,17 +56,29 @@ class F3_rs1rs2 : F3_rs1 {
set Inst{4-0} = rs2;
}
// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
class F3_rs1rs2rd : F3_rs1rs2 {
bits<5> rd;
set Inst{29-25} = rd;
set Inst{4-0} = rs2;
}
// F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
class F3_rs1simm13 : F3_rs1 {
bits<13> simm13;
set Inst{12-0} = simm13;
}
class F3_rs1simm13rd : F3_rs1simm13 {
bits<5> rd;
set Inst{29-25} = rd;
}
// Specific F3 classes...
//
class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
set op = opVal;
set op3 = op3val;
set Name = name;
@ -74,13 +86,33 @@ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
//set Inst{12-5} = dontcare;
}
class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
set op = opVal;
set op3 = op3val;
set Name = name;
set Inst{13} = 1; // i field = 1
}
#if 0
// The ordering is actually incorrect in these: in the assemble syntax,
// rd appears last!
class F3_1a<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
set op = opVal;
set op3 = op3val;
set Name = name;
set Inst{13} = 0; // i field = 0
//set Inst{12-5} = dontcare;
}
class F3_2a<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
set op = opVal;
set op3 = op3val;
set Name = name;
set Inst{13} = 1; // i field = 1
}
#endif
class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
set op = opVal;
set op3 = op3val;