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Factor out the code for sign-extending/truncating gep indices
and use it in x86 address mode folding. Also, make getRegForValue return 0 for illegal types even if it has a ValueMap for them, because Argument values are put in the ValueMap. This fixes PR3181. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60696 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -106,6 +106,11 @@ public:
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/// defined locally.
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unsigned lookUpRegForValue(Value *V);
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/// getRegForGEPIndex - This is a wrapper around getRegForValue that also
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/// takes care of truncating or sign-extending the given getelementptr
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/// index value.
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unsigned getRegForGEPIndex(Value *V);
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virtual ~FastISel();
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protected:
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@ -55,6 +55,19 @@
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using namespace llvm;
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unsigned FastISel::getRegForValue(Value *V) {
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MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
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// Ignore illegal types. We must do this before looking up the value
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// in ValueMap because Arguments are given virtual registers regardless
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// of whether FastISel can handle them.
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if (!TLI.isTypeLegal(VT)) {
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// Promote MVT::i1 to a legal type though, because it's common and easy.
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if (VT == MVT::i1)
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VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
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else
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return 0;
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}
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// Look up the value to see if we already have a register for it. We
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// cache values defined by Instructions across blocks, and other values
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// only locally. This is because Instructions already have the SSA
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@ -65,17 +78,6 @@ unsigned FastISel::getRegForValue(Value *V) {
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if (Reg != 0)
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return Reg;
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MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
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// Ignore illegal types.
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if (!TLI.isTypeLegal(VT)) {
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// Promote MVT::i1 to a legal type though, because it's common and easy.
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if (VT == MVT::i1)
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VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
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else
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return 0;
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}
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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if (CI->getValue().getActiveBits() <= 64)
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Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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@ -153,6 +155,24 @@ void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
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Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
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}
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unsigned FastISel::getRegForGEPIndex(Value *Idx) {
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unsigned IdxN = getRegForValue(Idx);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return 0;
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// If the index is smaller or larger than intptr_t, truncate or extend it.
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MVT PtrVT = TLI.getPointerTy();
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MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(PtrVT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
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ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(PtrVT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
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ISD::TRUNCATE, IdxN);
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return IdxN;
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}
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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@ -263,18 +283,7 @@ bool FastISel::SelectGetElementPtr(User *I) {
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getABITypeSize(Ty);
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unsigned IdxN = getRegForValue(Idx);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// If the index is smaller or larger than intptr_t, truncate or extend
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// it.
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MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(VT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(VT))
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IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
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unsigned IdxN = getRegForGEPIndex(Idx);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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@ -372,8 +372,8 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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unsigned IndexReg = AM.IndexReg;
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unsigned Scale = AM.Scale;
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gep_type_iterator GTI = gep_type_begin(U);
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// Look at all but the last index. Constants can be folded,
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// and one dynamic index can be handled, if the scale is supported.
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// Iterate through the indices, folding what we can. Constants can be
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// folded, and one dynamic index can be handled, if the scale is supported.
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for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
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i != e; ++i, ++GTI) {
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Value *Op = *i;
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@ -392,7 +392,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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(S == 1 || S == 2 || S == 4 || S == 8)) {
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// Scaled-index addressing.
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Scale = S;
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IndexReg = getRegForValue(Op);
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IndexReg = getRegForGEPIndex(Op);
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if (IndexReg == 0)
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return false;
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} else
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17
test/CodeGen/X86/fast-isel-gep-sext.ll
Normal file
17
test/CodeGen/X86/fast-isel-gep-sext.ll
Normal file
@ -0,0 +1,17 @@
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; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
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; RUN: llvm-as < %s | llc -march=x86 -fast
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; PR3181
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; GEP indices are interpreted as signed integers, so they
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; should be sign-extended to 64 bits on 64-bit targets.
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define i32 @foo(i32 %t3, i32* %t1) nounwind {
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%t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1]
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%t15 = load i32* %t9 ; <i32> [#uses=1]
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ret i32 %t15
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}
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define i32 @bar(i64 %t3, i32* %t1) nounwind {
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%t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1]
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%t15 = load i32* %t9 ; <i32> [#uses=1]
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ret i32 %t15
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}
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