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use simplified operand addition methods.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-30 01:01:54 +00:00
parent 9ce2e9d5a0
commit c8bd287f3c
2 changed files with 11 additions and 10 deletions
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4
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -469,8 +469,8 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
MI->addImmOperand(Pred[0].getImmedValue());
MI->addRegOperand(Pred[1].getReg(), false);
MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
return true;
}

17
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -126,7 +126,7 @@ bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
MBB.erase(MI);
}
PopMI->addRegOperand(Reg, true);
PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
}
return true;
}
@ -1100,9 +1100,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.setInstrDescriptor(TII.get(ARM::tLDR));
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
if (UseRR)
MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
else
MI.addRegOperand(0, false); // tLDR has an extra register operand.
// Use [reg, reg] addrmode.
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
else // tLDR has an extra register operand.
MI.addOperand(MachineOperand::CreateReg(0, false));
} else if (TII.isStore(Opcode)) {
// FIXME! This is horrific!!! We need register scavenging.
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
@ -1134,10 +1135,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
MI.setInstrDescriptor(TII.get(ARM::tSTR));
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
if (UseRR)
MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
else
MI.addRegOperand(0, false); // tSTR has an extra register operand.
if (UseRR) // Use [reg, reg] addrmode.
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
else // tSTR has an extra register operand.
MI.addOperand(MachineOperand::CreateReg(0, false));
MachineBasicBlock::iterator NII = next(II);
if (ValReg == ARM::R3)