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Implement support for promotion of AND/OR/XOR on integer types.

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The blackfin processor has a legal i16 type, but only logic operations on i32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75419 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2009-07-12 18:10:18 +00:00
parent 9a4ba45f4c
commit c8ca3ae27b
1 changed files with 19 additions and 8 deletions
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27
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3022,16 +3022,26 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
break; break;
case ISD::AND: case ISD::AND:
case ISD::OR: case ISD::OR:
case ISD::XOR: case ISD::XOR: {
assert(OVT.isVector() && "Don't know how to promote scalar logic ops"); unsigned ExtOp, TruncOp;
// Bit convert each of the values to the new type. if (OVT.isVector()) {
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); ExtOp = ISD::BIT_CONVERT;
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); TruncOp = ISD::BIT_CONVERT;
} else if (OVT.isInteger()) {
ExtOp = ISD::ANY_EXTEND;
TruncOp = ISD::TRUNCATE;
} else {
llvm_report_error("Cannot promote logic operation");
}
// Promote each of the values to the new type.
Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
// Perform the larger operation, then convert back
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
// Bit convert the result back the original type. Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1));
break; break;
case ISD::SELECT: }
case ISD::SELECT: {
unsigned ExtOp, TruncOp; unsigned ExtOp, TruncOp;
if (Node->getValueType(0).isVector()) { if (Node->getValueType(0).isVector()) {
ExtOp = ISD::BIT_CONVERT; ExtOp = ISD::BIT_CONVERT;
@ -3056,6 +3066,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
}
case ISD::VECTOR_SHUFFLE: { case ISD::VECTOR_SHUFFLE: {
SmallVector<int, 8> Mask; SmallVector<int, 8> Mask;
cast<ShuffleVectorSDNode>(Node)->getMask(Mask); cast<ShuffleVectorSDNode>(Node)->getMask(Mask);