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rearrange things a bit so that instructions can use subtarget features in the

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future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23902 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-23 22:08:13 +00:00
parent f690e6f3f6
commit c8d28890f6
1 changed files with 9 additions and 11 deletions
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20
lib/Target/PowerPC/PPC.td
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@ -15,16 +15,6 @@
//
include "../Target.td"
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "PPCRegisterInfo.td"
include "PPCSchedule.td"
include "PPCInstrInfo.td"
//===----------------------------------------------------------------------===//
// PowerPC Subtarget features.
//
@ -41,7 +31,15 @@ def FeatureFSqrt : SubtargetFeature<"fsqrt",
"Enable the fsqrt instruction">;
//===----------------------------------------------------------------------===//
// PowerPC chips sets supported.
// Register File Description
//===----------------------------------------------------------------------===//
include "PPCRegisterInfo.td"
include "PPCSchedule.td"
include "PPCInstrInfo.td"
//===----------------------------------------------------------------------===//
// PowerPC processors supported.
//
def : Processor<"generic", G3Itineraries, []>;