6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Clean up my own mess.

Browse Source 
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-03-12 07:02:50 +00:00
parent dfd07eab24
commit c8e3b147ee
3 changed files with 15 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
}
// fold (sub x, x) -> 0
if (N0 == N1) {
if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val))
// For example, zero vectors might be normalized to a particular vector
// type to ensure they are CSE'd. Avoid issuing zero vector nodes of
// *unexpected* type after legalization.
return N0;
if (N0 == N1)
return DAG.getConstant(0, N->getValueType(0));
}
// fold (sub c1, c2) -> c1-c2
if (N0C && N1C)
return DAG.getNode(ISD::SUB, VT, N0, N1);