mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Tidy up. 80 columns, whitespace, et. al.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1306,7 +1306,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, so_reg_reg:$shift),
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DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
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[(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
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[(set GPRnopc:$Rd, CPSR,
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(opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
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Requires<[IsARM]> {
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bits<4> Rd;
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bits<4> Rn;
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@ -1421,9 +1422,10 @@ multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
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// Note: We use the complex addrmode_imm12 rather than just an input
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// GPR and a constrained immediate so that we can use this to match
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// frame index references and avoid matching constant pool references.
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def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
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def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
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(ins addrmode_imm12:$addr),
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AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
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[(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
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[(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
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bits<4> Rt;
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bits<17> addr;
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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@ -1431,9 +1433,10 @@ multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
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AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
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[(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
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def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
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(ins ldst_so_reg:$shift),
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AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
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[(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
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bits<4> Rt;
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bits<17> shift;
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let shift{4} = 0; // Inst{4} = 0
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@ -1491,9 +1494,10 @@ multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
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AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
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[(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
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def rs : AI2ldst<0b011, 0, isByte, (outs),
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(ins GPRnopc:$Rt, ldst_so_reg:$shift),
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AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
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[(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
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bits<4> Rt;
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bits<17> shift;
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let shift{4} = 0; // Inst{4} = 0
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@ -3100,7 +3104,7 @@ class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{3-0} = Rm;
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let Unpredictable{11-8} = 0b1111;
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}
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@ -3394,25 +3398,26 @@ class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
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// property. Remove them when it's possible to add those properties
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// on an individual MachineInstr, not just an instuction description.
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let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
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def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
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IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
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[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
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Requires<[IsARM, HasV6]> {
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def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, GPRnopc:$Rm),
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IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
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[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{15-12} = 0b0000;
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let Unpredictable{15-12} = 0b1111;
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}
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let Constraints = "@earlyclobber $Rd" in
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def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
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pred:$p, cc_out:$s),
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4, IIC_iMUL32,
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[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
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(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
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Requires<[IsARM, NoV6]>;
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pred:$p, cc_out:$s),
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4, IIC_iMUL32,
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[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
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(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
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Requires<[IsARM, NoV6]>;
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}
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def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
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IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
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Requires<[IsARM, HasV6]> {
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bits<4> Ra;
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@ -3421,8 +3426,8 @@ def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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let Constraints = "@earlyclobber $Rd" in
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def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
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4, IIC_iMAC32,
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
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4, IIC_iMAC32,
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[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
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(MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
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Requires<[IsARM, NoV6]>;
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@ -4190,10 +4195,10 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
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// SWP/SWPB are deprecated in V6/V7.
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let mayLoad = 1, mayStore = 1 in {
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def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
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"swp", []>;
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def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
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"swpb", []>;
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def SWP : AIswp<0, (outs GPRnopc:$Rt),
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(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
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def SWPB: AIswp<1, (outs GPRnopc:$Rt),
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(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
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}
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//===----------------------------------------------------------------------===//
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@ -4519,8 +4524,8 @@ class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
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}
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def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2,
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imm:$CRm)]>;
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[(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
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GPRnopc:$Rt2, imm:$CRm)]>;
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def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
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class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
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@ -4547,8 +4552,8 @@ class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
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}
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def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2,
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imm:$CRm)]>;
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[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
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GPRnopc:$Rt2, imm:$CRm)]>;
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def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
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//===----------------------------------------------------------------------===//
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@ -4568,7 +4573,8 @@ def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
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let Unpredictable{11-0} = 0b110100001111;
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}
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def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, Requires<[IsARM]>;
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def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
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Requires<[IsARM]>;
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// The MRSsys instruction is the MRS instruction from the ARM ARM,
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// section B9.3.9, with the R bit set to 1.
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@ -1962,7 +1962,7 @@ def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
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let Inst{4} = Rn{5};
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}
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def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
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def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
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addrmode6oneL32> {
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let Inst{7} = lane{0};
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let Inst{5-4} = Rn{5-4};
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@ -5596,7 +5596,7 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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// extload, zextload and sextload for a standard lengthening load. Example:
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// Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr))
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// (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
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// (VMOVLuv8i16 (VLDRD addrmode5:$addr))>;
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multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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@ -5644,9 +5644,9 @@ multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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//
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)),
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// qsub_0)>;
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@ -5679,9 +5679,9 @@ multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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//
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// Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)),
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// dsub_0)>;
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@ -5944,17 +5944,17 @@ def VST2LNqWB_register_Asm_32 :
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// VLD3 all-lanes pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
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(ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD3DUPdWB_fixed_Asm_8 :
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@ -6220,17 +6220,17 @@ def VST3qWB_register_Asm_32 :
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// VLD4 all-lanes pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdWB_fixed_Asm_8 :
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@ -3622,8 +3622,8 @@ defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
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// A/R class MRS.
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//
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// A/R class can only move from CPSR or SPSR.
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def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
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Requires<[IsThumb2,IsARClass]> {
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def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
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[]>, Requires<[IsThumb2,IsARClass]> {
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bits<4> Rd;
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let Inst{31-12} = 0b11110011111011111000;
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let Inst{11-8} = Rd;
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@ -3632,8 +3632,8 @@ def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>
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def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
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def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
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Requires<[IsThumb2,IsARClass]> {
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def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
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[]>, Requires<[IsThumb2,IsARClass]> {
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bits<4> Rd;
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let Inst{31-12} = 0b11110011111111111000;
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let Inst{11-8} = Rd;
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@ -827,9 +827,9 @@ let Constraints = "$a = $dst" in {
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// FP to Fixed-Point:
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// Single Precision register
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class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
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dag oops, dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
|
||||
bit op5, dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, list<dag> pattern>
|
||||
: AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
|
||||
bits<5> dst;
|
||||
// if dp_operation then UInt(D:Vd) else UInt(Vd:D);
|
||||
@ -838,9 +838,9 @@ class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bi
|
||||
}
|
||||
|
||||
// Double Precision register
|
||||
class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
|
||||
dag oops, dag iops, InstrItinClass itin, string opc, string asm,
|
||||
list<dag> pattern>
|
||||
class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
|
||||
bit op5, dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, list<dag> pattern>
|
||||
: AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
|
||||
bits<5> dst;
|
||||
// if dp_operation then UInt(D:Vd) else UInt(Vd:D);
|
||||
|
Loading…
Reference in New Issue
Block a user