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Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -184,8 +184,6 @@ public:
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/// incorporating info about the result values into this state.
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/// incorporating info about the result values into this state.
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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CCAssignFn Fn);
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
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CCAssignFn Fn);
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/// CheckReturn - Analyze the return values of a function, returning
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/// CheckReturn - Analyze the return values of a function, returning
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/// true if the return can be performed without sret-demotion, and
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/// true if the return can be performed without sret-demotion, and
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@ -198,8 +196,6 @@ public:
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/// incorporating info about the passed values into this state.
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/// incorporating info about the passed values into this state.
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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CCAssignFn Fn);
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
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CCAssignFn Fn);
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/// AnalyzeCallOperands - Same as above except it takes vectors of types
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/// AnalyzeCallOperands - Same as above except it takes vectors of types
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/// and argument flags.
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/// and argument flags.
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@ -14,8 +14,6 @@
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#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
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#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
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#define LLVM_TARGET_TARGETCALLINGCONV_H
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#define LLVM_TARGET_TARGETCALLINGCONV_H
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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namespace llvm {
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namespace ISD {
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namespace ISD {
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@ -112,7 +110,7 @@ namespace ISD {
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bool Used;
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bool Used;
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InputArg() : VT(MVT::Other), Used(false) {}
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InputArg() : VT(MVT::Other), Used(false) {}
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InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
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InputArg(ArgFlagsTy flags, EVT vt, bool used)
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: Flags(flags), VT(vt), Used(used) {
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: Flags(flags), VT(vt), Used(used) {
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assert(VT.isSimple() &&
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assert(VT.isSimple() &&
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"InputArg value type must be Simple!");
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"InputArg value type must be Simple!");
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@ -125,35 +123,18 @@ namespace ISD {
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///
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///
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struct OutputArg {
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struct OutputArg {
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ArgFlagsTy Flags;
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ArgFlagsTy Flags;
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SDValue Val;
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EVT VT;
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/// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
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/// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
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bool IsFixed;
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bool IsFixed;
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OutputArg() : IsFixed(false) {}
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OutputArg() : IsFixed(false) {}
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OutputArg(ISD::ArgFlagsTy flags, SDValue val, bool isfixed)
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OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
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: Flags(flags), Val(val), IsFixed(isfixed) {
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: Flags(flags), VT(vt), IsFixed(isfixed) {
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assert(Val.getValueType().isSimple() &&
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assert(VT.isSimple() &&
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"OutputArg value type must be Simple!");
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"OutputArg value type must be Simple!");
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}
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}
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};
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};
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/// OutputArgReg - This struct carries flags and a register value for a
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/// single outgoing (actual) argument or outgoing (from the perspective
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/// of the caller) return value virtual register.
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///
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struct OutputArgReg {
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ArgFlagsTy Flags;
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EVT VT;
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unsigned Reg;
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/// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
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bool IsFixed;
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OutputArgReg() : IsFixed(false) {}
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OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed)
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: Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {}
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};
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}
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}
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} // end llvm namespace
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} // end llvm namespace
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@ -1145,6 +1145,7 @@ public:
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LowerCall(SDValue Chain, SDValue Callee,
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
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CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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SmallVectorImpl<SDValue> &InVals) const {
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@ -1173,6 +1174,7 @@ public:
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virtual SDValue
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virtual SDValue
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LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const {
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DebugLoc dl, SelectionDAG &DAG) const {
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assert(0 && "Not Implemented");
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assert(0 && "Not Implemented");
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return SDValue(); // this is here to silence compiler errors
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return SDValue(); // this is here to silence compiler errors
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@ -98,22 +98,6 @@ bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
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void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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EVT VT = Outs[i].Val.getValueType();
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Return operand #" << i << " has unhandled type "
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<< VT.getEVTString();
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#endif
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llvm_unreachable(0);
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}
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}
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}
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void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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EVT VT = Outs[i].VT;
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EVT VT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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@ -127,31 +111,11 @@ void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
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}
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}
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}
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}
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// incorporating info about the passed values into this state.
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/// incorporating info about the passed values into this state.
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void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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CCAssignFn Fn) {
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unsigned NumOps = Outs.size();
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unsigned NumOps = Outs.size();
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for (unsigned i = 0; i != NumOps; ++i) {
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EVT ArgVT = Outs[i].Val.getValueType();
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call operand #" << i << " has unhandled type "
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<< ArgVT.getEVTString();
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#endif
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llvm_unreachable(0);
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}
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}
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}
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// incorporating info about the passed values into this state.
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void
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CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
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CCAssignFn Fn) {
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unsigned NumOps = Outs.size();
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for (unsigned i = 0; i != NumOps; ++i) {
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for (unsigned i = 0; i != NumOps; ++i) {
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EVT ArgVT = Outs[i].VT;
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EVT ArgVT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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@ -1027,6 +1027,7 @@ static void getReturnInfo(const Type* ReturnType,
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void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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SDValue Chain = getControlRoot();
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SDValue Chain = getControlRoot();
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SmallVector<ISD::OutputArg, 8> Outs;
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SmallVector<ISD::OutputArg, 8> Outs;
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SmallVector<SDValue, 8> OutVals;
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if (!FuncInfo.CanLowerReturn) {
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if (!FuncInfo.CanLowerReturn) {
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unsigned DemoteReg = FuncInfo.DemoteRegister;
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unsigned DemoteReg = FuncInfo.DemoteRegister;
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@ -1105,8 +1106,11 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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else if (F->paramHasAttr(0, Attribute::ZExt))
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else if (F->paramHasAttr(0, Attribute::ZExt))
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Flags.setZExt();
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Flags.setZExt();
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for (unsigned i = 0; i < NumParts; ++i)
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for (unsigned i = 0; i < NumParts; ++i) {
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Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
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Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
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/*isfixed=*/true));
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OutVals.push_back(Parts[i]);
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}
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}
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}
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}
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}
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}
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}
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@ -1115,7 +1119,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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CallingConv::ID CallConv =
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CallingConv::ID CallConv =
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DAG.getMachineFunction().getFunction()->getCallingConv();
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DAG.getMachineFunction().getFunction()->getCallingConv();
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Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
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Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
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Outs, getCurDebugLoc(), DAG);
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Outs, OutVals, getCurDebugLoc(), DAG);
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// Verify that the target's LowerReturn behaved as expected.
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// Verify that the target's LowerReturn behaved as expected.
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assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
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assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
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@ -5768,6 +5772,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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DebugLoc dl) const {
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DebugLoc dl) const {
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// Handle all of the outgoing arguments.
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// Handle all of the outgoing arguments.
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SmallVector<ISD::OutputArg, 32> Outs;
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SmallVector<ISD::OutputArg, 32> Outs;
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SmallVector<SDValue, 32> OutVals;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
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ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
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@ -5821,13 +5826,15 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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for (unsigned j = 0; j != NumParts; ++j) {
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for (unsigned j = 0; j != NumParts; ++j) {
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// if it isn't first piece, alignment must be 1
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// if it isn't first piece, alignment must be 1
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ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
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ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
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i < NumFixedArgs);
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if (NumParts > 1 && j == 0)
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if (NumParts > 1 && j == 0)
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MyFlags.Flags.setSplit();
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MyFlags.Flags.setSplit();
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else if (j != 0)
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else if (j != 0)
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MyFlags.Flags.setOrigAlign(1);
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MyFlags.Flags.setOrigAlign(1);
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Outs.push_back(MyFlags);
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Outs.push_back(MyFlags);
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OutVals.push_back(Parts[j]);
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}
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}
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}
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}
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}
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}
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@ -5856,7 +5863,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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SmallVector<SDValue, 4> InVals;
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SmallVector<SDValue, 4> InVals;
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Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
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Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
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Outs, Ins, dl, DAG, InVals);
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Outs, OutVals, Ins, dl, DAG, InVals);
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// Verify that the target's LowerCall behaved as expected.
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// Verify that the target's LowerCall behaved as expected.
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assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
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assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
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@ -1030,6 +1030,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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SmallVectorImpl<SDValue> &InVals) const {
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@ -1043,7 +1044,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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// Check if it's really possible to do a tail call.
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// Check if it's really possible to do a tail call.
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
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isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
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isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
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Outs, Ins, DAG);
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Outs, OutVals, Ins, DAG);
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// We don't support GuaranteedTailCallOpt for ARM, only automatically
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// We don't support GuaranteedTailCallOpt for ARM, only automatically
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// detected sibcalls.
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// detected sibcalls.
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if (isTailCall) {
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if (isTailCall) {
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@ -1083,7 +1084,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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i != e;
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i != e;
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++i, ++realArgIdx) {
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++i, ++realArgIdx) {
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CCValAssign &VA = ArgLocs[i];
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = Outs[realArgIdx].Val;
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SDValue Arg = OutVals[realArgIdx];
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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// Promote the value if needed.
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// Promote the value if needed.
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@ -1377,6 +1378,7 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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bool isCalleeStructRet,
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bool isCalleeStructRet,
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bool isCallerStructRet,
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bool isCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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SelectionDAG& DAG) const {
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const Function *CallerF = DAG.getMachineFunction().getFunction();
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const Function *CallerF = DAG.getMachineFunction().getFunction();
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@ -1470,7 +1472,7 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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++i, ++realArgIdx) {
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++i, ++realArgIdx) {
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CCValAssign &VA = ArgLocs[i];
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CCValAssign &VA = ArgLocs[i];
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EVT RegVT = VA.getLocVT();
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EVT RegVT = VA.getLocVT();
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SDValue Arg = Outs[realArgIdx].Val;
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SDValue Arg = OutVals[realArgIdx];
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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if (VA.getLocInfo() == CCValAssign::Indirect)
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if (VA.getLocInfo() == CCValAssign::Indirect)
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return false;
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return false;
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@ -1505,6 +1507,7 @@ SDValue
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ARMTargetLowering::LowerReturn(SDValue Chain,
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ARMTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const {
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DebugLoc dl, SelectionDAG &DAG) const {
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// CCValAssign - represent the assignment of the return value to a location.
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// CCValAssign - represent the assignment of the return value to a location.
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@ -1535,7 +1538,7 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
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CCValAssign &VA = RVLocs[i];
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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assert(VA.isRegLoc() && "Can only return in registers!");
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|
||||||
SDValue Arg = Outs[realRVLocIdx].Val;
|
SDValue Arg = OutVals[realRVLocIdx];
|
||||||
|
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
default: llvm_unreachable("Unknown loc info!");
|
default: llvm_unreachable("Unknown loc info!");
|
||||||
|
@ -337,6 +337,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -350,12 +351,14 @@ namespace llvm {
|
|||||||
bool isCalleeStructRet,
|
bool isCalleeStructRet,
|
||||||
bool isCallerStructRet,
|
bool isCallerStructRet,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
SelectionDAG& DAG) const;
|
SelectionDAG& DAG) const;
|
||||||
virtual SDValue
|
virtual SDValue
|
||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||||
|
@ -224,6 +224,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -251,7 +252,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -470,6 +471,7 @@ SDValue
|
|||||||
AlphaTargetLowering::LowerReturn(SDValue Chain,
|
AlphaTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
|
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
|
||||||
@ -483,7 +485,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
break;
|
break;
|
||||||
//return SDValue(); // ret void is legal
|
//return SDValue(); // ret void is legal
|
||||||
case 1: {
|
case 1: {
|
||||||
EVT ArgVT = Outs[0].Val.getValueType();
|
EVT ArgVT = Outs[0].VT;
|
||||||
unsigned ArgReg;
|
unsigned ArgReg;
|
||||||
if (ArgVT.isInteger())
|
if (ArgVT.isInteger())
|
||||||
ArgReg = Alpha::R0;
|
ArgReg = Alpha::R0;
|
||||||
@ -492,13 +494,13 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
ArgReg = Alpha::F0;
|
ArgReg = Alpha::F0;
|
||||||
}
|
}
|
||||||
Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
|
Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
|
||||||
Outs[0].Val, Copy.getValue(1));
|
OutVals[0], Copy.getValue(1));
|
||||||
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
|
||||||
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
|
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case 2: {
|
case 2: {
|
||||||
EVT ArgVT = Outs[0].Val.getValueType();
|
EVT ArgVT = Outs[0].VT;
|
||||||
unsigned ArgReg1, ArgReg2;
|
unsigned ArgReg1, ArgReg2;
|
||||||
if (ArgVT.isInteger()) {
|
if (ArgVT.isInteger()) {
|
||||||
ArgReg1 = Alpha::R0;
|
ArgReg1 = Alpha::R0;
|
||||||
@ -509,13 +511,13 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
ArgReg2 = Alpha::F1;
|
ArgReg2 = Alpha::F1;
|
||||||
}
|
}
|
||||||
Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
|
Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
|
||||||
Outs[0].Val, Copy.getValue(1));
|
OutVals[0], Copy.getValue(1));
|
||||||
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
|
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
|
||||||
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
|
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
|
||||||
== DAG.getMachineFunction().getRegInfo().liveout_end())
|
== DAG.getMachineFunction().getRegInfo().liveout_end())
|
||||||
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
|
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
|
||||||
Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
|
Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
|
||||||
Outs[1].Val, Copy.getValue(1));
|
OutVals[1], Copy.getValue(1));
|
||||||
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
|
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
|
||||||
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
|
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
|
||||||
== DAG.getMachineFunction().getRegInfo().liveout_end())
|
== DAG.getMachineFunction().getRegInfo().liveout_end())
|
||||||
|
@ -121,6 +121,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -129,6 +130,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
@ -219,6 +219,7 @@ SDValue
|
|||||||
BlackfinTargetLowering::LowerReturn(SDValue Chain,
|
BlackfinTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of the return value to locations.
|
// CCValAssign - represent the assignment of the return value to locations.
|
||||||
@ -244,7 +245,7 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
||||||
CCValAssign &VA = RVLocs[i];
|
CCValAssign &VA = RVLocs[i];
|
||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
SDValue Opi = Outs[i].Val;
|
SDValue Opi = OutVals[i];
|
||||||
|
|
||||||
// Expand to i32 if necessary
|
// Expand to i32 if necessary
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -277,6 +278,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -300,7 +302,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
// Walk the register/memloc assignments, inserting copies/loads.
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
|
@ -63,6 +63,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -71,6 +72,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
};
|
};
|
||||||
} // end namespace llvm
|
} // end namespace llvm
|
||||||
|
@ -1135,6 +1135,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -1166,7 +1167,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
SmallVector<SDValue, 8> MemOpChains;
|
SmallVector<SDValue, 8> MemOpChains;
|
||||||
|
|
||||||
for (unsigned i = 0; i != NumOps; ++i) {
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// PtrOff will be used to store the current argument to the stack if a
|
// PtrOff will be used to store the current argument to the stack if a
|
||||||
// register cannot be found for it.
|
// register cannot be found for it.
|
||||||
@ -1339,6 +1340,7 @@ SDValue
|
|||||||
SPUTargetLowering::LowerReturn(SDValue Chain,
|
SPUTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
SmallVector<CCValAssign, 16> RVLocs;
|
SmallVector<CCValAssign, 16> RVLocs;
|
||||||
@ -1360,7 +1362,7 @@ SPUTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
CCValAssign &VA = RVLocs[i];
|
CCValAssign &VA = RVLocs[i];
|
||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -159,6 +159,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -167,6 +168,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
@ -525,6 +525,7 @@ SDValue MBlazeTargetLowering::
|
|||||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||||
bool isVarArg, bool &isTailCall,
|
bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -556,7 +557,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
|||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
EVT RegVT = VA.getLocVT();
|
EVT RegVT = VA.getLocVT();
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -835,6 +836,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|||||||
SDValue MBlazeTargetLowering::
|
SDValue MBlazeTargetLowering::
|
||||||
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
// CCValAssign - represent the assignment of
|
// CCValAssign - represent the assignment of
|
||||||
// the return value to a location
|
// the return value to a location
|
||||||
@ -863,7 +865,7 @@ LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
|
|
||||||
// guarantee that all emitted copies are
|
// guarantee that all emitted copies are
|
||||||
// stuck together, avoiding something bad
|
// stuck together, avoiding something bad
|
||||||
|
@ -109,6 +109,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -117,6 +118,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
virtual MachineBasicBlock *
|
virtual MachineBasicBlock *
|
||||||
|
@ -278,6 +278,7 @@ MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -290,7 +291,7 @@ MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
case CallingConv::Fast:
|
case CallingConv::Fast:
|
||||||
case CallingConv::C:
|
case CallingConv::C:
|
||||||
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
||||||
Outs, Ins, dl, DAG, InVals);
|
Outs, OutVals, Ins, dl, DAG, InVals);
|
||||||
case CallingConv::MSP430_INTR:
|
case CallingConv::MSP430_INTR:
|
||||||
report_fatal_error("ISRs cannot be called directly");
|
report_fatal_error("ISRs cannot be called directly");
|
||||||
return SDValue();
|
return SDValue();
|
||||||
@ -387,6 +388,7 @@ SDValue
|
|||||||
MSP430TargetLowering::LowerReturn(SDValue Chain,
|
MSP430TargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of the return value to a location
|
// CCValAssign - represent the assignment of the return value to a location
|
||||||
@ -421,7 +423,7 @@ MSP430TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
|
|
||||||
// Guarantee that all emitted copies are stuck together,
|
// Guarantee that all emitted copies are stuck together,
|
||||||
// avoiding something bad.
|
// avoiding something bad.
|
||||||
@ -447,6 +449,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg>
|
const SmallVectorImpl<ISD::OutputArg>
|
||||||
&Outs,
|
&Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -471,7 +474,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
|
@ -127,6 +127,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -155,6 +156,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -163,6 +165,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
||||||
|
@ -767,6 +767,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -807,7 +808,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
|
|
||||||
// Walk the register/memloc assignments, inserting copies/loads.
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
@ -1168,6 +1169,7 @@ SDValue
|
|||||||
MipsTargetLowering::LowerReturn(SDValue Chain,
|
MipsTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of
|
// CCValAssign - represent the assignment of
|
||||||
@ -1197,7 +1199,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
|
|
||||||
// guarantee that all emitted copies are
|
// guarantee that all emitted copies are
|
||||||
// stuck together, avoiding something bad
|
// stuck together, avoiding something bad
|
||||||
|
@ -120,6 +120,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -128,6 +129,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
virtual MachineBasicBlock *
|
virtual MachineBasicBlock *
|
||||||
|
@ -1121,6 +1121,7 @@ SDValue PIC16TargetLowering::
|
|||||||
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
||||||
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
|
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
unsigned NumOps = Outs.size();
|
unsigned NumOps = Outs.size();
|
||||||
@ -1137,7 +1138,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
|||||||
unsigned RetVals = Ins.size();
|
unsigned RetVals = Ins.size();
|
||||||
for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
|
for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
|
||||||
// Get the arguments
|
// Get the arguments
|
||||||
Arg = Outs[i].Val;
|
Arg = OutVals[i];
|
||||||
|
|
||||||
Ops.clear();
|
Ops.clear();
|
||||||
Ops.push_back(Chain);
|
Ops.push_back(Chain);
|
||||||
@ -1159,6 +1160,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
|||||||
SDValue PIC16TargetLowering::
|
SDValue PIC16TargetLowering::
|
||||||
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
|
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
unsigned NumOps = Outs.size();
|
unsigned NumOps = Outs.size();
|
||||||
std::string Name;
|
std::string Name;
|
||||||
@ -1184,7 +1186,7 @@ LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
|
|||||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||||
for (unsigned i=0, Offset = 0; i<NumOps; i++) {
|
for (unsigned i=0, Offset = 0; i<NumOps; i++) {
|
||||||
// Get the argument
|
// Get the argument
|
||||||
Arg = Outs[i].Val;
|
Arg = OutVals[i];
|
||||||
StoreOffset = (Offset + AddressOffset);
|
StoreOffset = (Offset + AddressOffset);
|
||||||
|
|
||||||
// Store the argument on frame
|
// Store the argument on frame
|
||||||
@ -1283,6 +1285,7 @@ SDValue
|
|||||||
PIC16TargetLowering::LowerReturn(SDValue Chain,
|
PIC16TargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// Number of values to return
|
// Number of values to return
|
||||||
@ -1299,7 +1302,7 @@ PIC16TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
SDValue BS = DAG.getConstant(1, MVT::i8);
|
SDValue BS = DAG.getConstant(1, MVT::i8);
|
||||||
SDValue RetVal;
|
SDValue RetVal;
|
||||||
for(unsigned i=0;i<NumRet; ++i) {
|
for(unsigned i=0;i<NumRet; ++i) {
|
||||||
RetVal = Outs[i].Val;
|
RetVal = OutVals[i];
|
||||||
Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
|
Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
|
||||||
ES, BS,
|
ES, BS,
|
||||||
DAG.getConstant (i, MVT::i8));
|
DAG.getConstant (i, MVT::i8));
|
||||||
@ -1375,6 +1378,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -1462,12 +1466,13 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
SDValue CallArgs;
|
SDValue CallArgs;
|
||||||
if (IsDirectCall) {
|
if (IsDirectCall) {
|
||||||
CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
|
CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
|
||||||
Outs, dl, DAG);
|
Outs, OutVals, dl, DAG);
|
||||||
Chain = getChain(CallArgs);
|
Chain = getChain(CallArgs);
|
||||||
OperFlag = getOutFlag(CallArgs);
|
OperFlag = getOutFlag(CallArgs);
|
||||||
} else {
|
} else {
|
||||||
CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
|
CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
|
||||||
DataAddr_Hi, Outs, Ins, dl, DAG);
|
DataAddr_Hi, Outs, OutVals, Ins,
|
||||||
|
dl, DAG);
|
||||||
Chain = getChain(CallArgs);
|
Chain = getChain(CallArgs);
|
||||||
OperFlag = getOutFlag(CallArgs);
|
OperFlag = getOutFlag(CallArgs);
|
||||||
}
|
}
|
||||||
|
@ -106,12 +106,14 @@ namespace llvm {
|
|||||||
SDValue
|
SDValue
|
||||||
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
|
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
|
||||||
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
|
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
@ -143,6 +145,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -151,6 +154,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue ExpandStore(SDNode *N, SelectionDAG &DAG) const;
|
SDValue ExpandStore(SDNode *N, SelectionDAG &DAG) const;
|
||||||
|
@ -2136,6 +2136,7 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
|
|||||||
unsigned CC,
|
unsigned CC,
|
||||||
const SmallVectorImpl<ISD::OutputArg>
|
const SmallVectorImpl<ISD::OutputArg>
|
||||||
&Outs,
|
&Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
unsigned &nAltivecParamsAtEnd) {
|
unsigned &nAltivecParamsAtEnd) {
|
||||||
// Count how many bytes are to be pushed on the stack, including the linkage
|
// Count how many bytes are to be pushed on the stack, including the linkage
|
||||||
// area, and parameter passing area. We start with 24/48 bytes, which is
|
// area, and parameter passing area. We start with 24/48 bytes, which is
|
||||||
@ -2152,9 +2153,9 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
|
|||||||
// 16-byte aligned.
|
// 16-byte aligned.
|
||||||
nAltivecParamsAtEnd = 0;
|
nAltivecParamsAtEnd = 0;
|
||||||
for (unsigned i = 0; i != NumOps; ++i) {
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
EVT ArgVT = Arg.getValueType();
|
EVT ArgVT = Outs[i].VT;
|
||||||
// Varargs Altivec parameters are padded to a 16 byte boundary.
|
// Varargs Altivec parameters are padded to a 16 byte boundary.
|
||||||
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
|
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
|
||||||
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
|
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
|
||||||
@ -2704,6 +2705,7 @@ PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -2713,11 +2715,11 @@ PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
|
|
||||||
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
|
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
|
||||||
return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
|
return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
|
||||||
isTailCall, Outs, Ins,
|
isTailCall, Outs, OutVals, Ins,
|
||||||
dl, DAG, InVals);
|
dl, DAG, InVals);
|
||||||
} else {
|
} else {
|
||||||
return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
|
return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
|
||||||
isTailCall, Outs, Ins,
|
isTailCall, Outs, OutVals, Ins,
|
||||||
dl, DAG, InVals);
|
dl, DAG, InVals);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2727,6 +2729,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -2767,7 +2770,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
|||||||
unsigned NumArgs = Outs.size();
|
unsigned NumArgs = Outs.size();
|
||||||
|
|
||||||
for (unsigned i = 0; i != NumArgs; ++i) {
|
for (unsigned i = 0; i != NumArgs; ++i) {
|
||||||
EVT ArgVT = Outs[i].Val.getValueType();
|
EVT ArgVT = Outs[i].VT;
|
||||||
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
|
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
|
||||||
bool Result;
|
bool Result;
|
||||||
|
|
||||||
@ -2836,7 +2839,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
|||||||
i != e;
|
i != e;
|
||||||
++i) {
|
++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
|
|
||||||
if (Flags.isByVal()) {
|
if (Flags.isByVal()) {
|
||||||
@ -2932,6 +2935,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -2959,7 +2963,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|||||||
// prereserved space for [SP][CR][LR][3 x unused].
|
// prereserved space for [SP][CR][LR][3 x unused].
|
||||||
unsigned NumBytes =
|
unsigned NumBytes =
|
||||||
CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
|
CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
|
||||||
Outs,
|
Outs, OutVals,
|
||||||
nAltivecParamsAtEnd);
|
nAltivecParamsAtEnd);
|
||||||
|
|
||||||
// Calculate by how many bytes the stack has to be adjusted in case of tail
|
// Calculate by how many bytes the stack has to be adjusted in case of tail
|
||||||
@ -3023,7 +3027,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|||||||
|
|
||||||
SmallVector<SDValue, 8> MemOpChains;
|
SmallVector<SDValue, 8> MemOpChains;
|
||||||
for (unsigned i = 0; i != NumOps; ++i) {
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
|
|
||||||
// PtrOff will be used to store the current argument to the stack if a
|
// PtrOff will be used to store the current argument to the stack if a
|
||||||
@ -3226,8 +3230,8 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|||||||
ArgOffset = ((ArgOffset+15)/16)*16;
|
ArgOffset = ((ArgOffset+15)/16)*16;
|
||||||
ArgOffset += 12*16;
|
ArgOffset += 12*16;
|
||||||
for (unsigned i = 0; i != NumOps; ++i) {
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
EVT ArgType = Arg.getValueType();
|
EVT ArgType = Outs[i].VT;
|
||||||
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
|
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
|
||||||
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
|
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
|
||||||
if (++j > NumVRs) {
|
if (++j > NumVRs) {
|
||||||
@ -3295,6 +3299,7 @@ SDValue
|
|||||||
PPCTargetLowering::LowerReturn(SDValue Chain,
|
PPCTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
SmallVector<CCValAssign, 16> RVLocs;
|
SmallVector<CCValAssign, 16> RVLocs;
|
||||||
@ -3316,7 +3321,7 @@ PPCTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
CCValAssign &VA = RVLocs[i];
|
CCValAssign &VA = RVLocs[i];
|
||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -435,6 +435,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -443,6 +444,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -462,6 +464,7 @@ namespace llvm {
|
|||||||
LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -469,6 +472,7 @@ namespace llvm {
|
|||||||
LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
|
@ -38,6 +38,7 @@ SDValue
|
|||||||
SparcTargetLowering::LowerReturn(SDValue Chain,
|
SparcTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of the return value to locations.
|
// CCValAssign - represent the assignment of the return value to locations.
|
||||||
@ -66,7 +67,7 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
|
|
||||||
// Guarantee that all emitted copies are stuck together with flags.
|
// Guarantee that all emitted copies are stuck together with flags.
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
@ -262,6 +263,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -283,7 +285,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
// Count the size of the outgoing arguments.
|
// Count the size of the outgoing arguments.
|
||||||
unsigned ArgsSize = 0;
|
unsigned ArgsSize = 0;
|
||||||
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
||||||
switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
|
switch (Outs[i].VT.getSimpleVT().SimpleTy) {
|
||||||
default: llvm_unreachable("Unknown value type!");
|
default: llvm_unreachable("Unknown value type!");
|
||||||
case MVT::i1:
|
case MVT::i1:
|
||||||
case MVT::i8:
|
case MVT::i8:
|
||||||
@ -316,7 +318,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
// Walk the register/memloc assignments, inserting copies/loads.
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -358,8 +360,8 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
unsigned ArgOffset = 68;
|
unsigned ArgOffset = 68;
|
||||||
|
|
||||||
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
||||||
SDValue Val = Outs[i].Val;
|
SDValue Val = OutVals[i];
|
||||||
EVT ObjectVT = Val.getValueType();
|
EVT ObjectVT = Outs[i].VT;
|
||||||
SDValue ValToStore(0, 0);
|
SDValue ValToStore(0, 0);
|
||||||
unsigned ObjSize;
|
unsigned ObjSize;
|
||||||
switch (ObjectVT.getSimpleVT().SimpleTy) {
|
switch (ObjectVT.getSimpleVT().SimpleTy) {
|
||||||
|
@ -86,6 +86,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -94,6 +95,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||||
|
@ -254,6 +254,7 @@ SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -266,7 +267,7 @@ SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
case CallingConv::Fast:
|
case CallingConv::Fast:
|
||||||
case CallingConv::C:
|
case CallingConv::C:
|
||||||
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
||||||
Outs, Ins, dl, DAG, InVals);
|
Outs, OutVals, Ins, dl, DAG, InVals);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -372,6 +373,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg>
|
const SmallVectorImpl<ISD::OutputArg>
|
||||||
&Outs,
|
&Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -402,7 +404,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -550,6 +552,7 @@ SDValue
|
|||||||
SystemZTargetLowering::LowerReturn(SDValue Chain,
|
SystemZTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of the return value to a location
|
// CCValAssign - represent the assignment of the return value to a location
|
||||||
@ -575,7 +578,7 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
// Copy the result values into the output registers.
|
// Copy the result values into the output registers.
|
||||||
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
||||||
CCValAssign &VA = RVLocs[i];
|
CCValAssign &VA = RVLocs[i];
|
||||||
SDValue ResValue = Outs[i].Val;
|
SDValue ResValue = OutVals[i];
|
||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
// If this is an 8/16/32-bit value, it is really should be passed promoted
|
// If this is an 8/16/32-bit value, it is really should be passed promoted
|
||||||
|
@ -98,6 +98,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -126,6 +127,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -134,6 +136,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
const SystemZSubtarget &Subtarget;
|
const SystemZSubtarget &Subtarget;
|
||||||
|
@ -1231,6 +1231,7 @@ SDValue
|
|||||||
X86TargetLowering::LowerReturn(SDValue Chain,
|
X86TargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
MachineFunction &MF = DAG.getMachineFunction();
|
MachineFunction &MF = DAG.getMachineFunction();
|
||||||
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
||||||
@ -1258,7 +1259,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
||||||
CCValAssign &VA = RVLocs[i];
|
CCValAssign &VA = RVLocs[i];
|
||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
SDValue ValToCopy = Outs[i].Val;
|
SDValue ValToCopy = OutVals[i];
|
||||||
|
|
||||||
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
|
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
|
||||||
// the RET instruction and handled by the FP Stackifier.
|
// the RET instruction and handled by the FP Stackifier.
|
||||||
@ -1816,6 +1817,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -1828,7 +1830,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
// Check if it's really possible to do a tail call.
|
// Check if it's really possible to do a tail call.
|
||||||
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
|
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
|
||||||
isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
|
isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
|
||||||
Outs, Ins, DAG);
|
Outs, OutVals, Ins, DAG);
|
||||||
|
|
||||||
// Sibcalls are automatically detected tailcalls which do not require
|
// Sibcalls are automatically detected tailcalls which do not require
|
||||||
// ABI changes.
|
// ABI changes.
|
||||||
@ -1888,7 +1890,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
EVT RegVT = VA.getLocVT();
|
EVT RegVT = VA.getLocVT();
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
bool isByVal = Flags.isByVal();
|
bool isByVal = Flags.isByVal();
|
||||||
|
|
||||||
@ -2027,7 +2029,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
if (VA.isRegLoc())
|
if (VA.isRegLoc())
|
||||||
continue;
|
continue;
|
||||||
assert(VA.isMemLoc());
|
assert(VA.isMemLoc());
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
// Create frame index.
|
// Create frame index.
|
||||||
int32_t Offset = VA.getLocMemOffset()+FPDiff;
|
int32_t Offset = VA.getLocMemOffset()+FPDiff;
|
||||||
@ -2320,6 +2322,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
|
|||||||
bool isCalleeStructRet,
|
bool isCalleeStructRet,
|
||||||
bool isCallerStructRet,
|
bool isCallerStructRet,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
SelectionDAG& DAG) const {
|
SelectionDAG& DAG) const {
|
||||||
if (!IsTailCallConvention(CalleeCC) &&
|
if (!IsTailCallConvention(CalleeCC) &&
|
||||||
@ -2433,7 +2436,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
|
|||||||
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
|
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
||||||
if (VA.getLocInfo() == CCValAssign::Indirect)
|
if (VA.getLocInfo() == CCValAssign::Indirect)
|
||||||
return false;
|
return false;
|
||||||
|
@ -652,6 +652,7 @@ namespace llvm {
|
|||||||
bool isCalleeStructRet,
|
bool isCalleeStructRet,
|
||||||
bool isCallerStructRet,
|
bool isCallerStructRet,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
SelectionDAG& DAG) const;
|
SelectionDAG& DAG) const;
|
||||||
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
||||||
@ -734,6 +735,7 @@ namespace llvm {
|
|||||||
LowerCall(SDValue Chain, SDValue Callee,
|
LowerCall(SDValue Chain, SDValue Callee,
|
||||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -742,6 +744,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
virtual bool
|
virtual bool
|
||||||
|
@ -812,6 +812,7 @@ XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -826,7 +827,7 @@ XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
|||||||
case CallingConv::Fast:
|
case CallingConv::Fast:
|
||||||
case CallingConv::C:
|
case CallingConv::C:
|
||||||
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
|
||||||
Outs, Ins, dl, DAG, InVals);
|
Outs, OutVals, Ins, dl, DAG, InVals);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -839,6 +840,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
@ -866,7 +868,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
// Walk the register/memloc assignments, inserting copies/loads.
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
SDValue Arg = Outs[i].Val;
|
SDValue Arg = OutVals[i];
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
switch (VA.getLocInfo()) {
|
switch (VA.getLocInfo()) {
|
||||||
@ -1146,6 +1148,7 @@ SDValue
|
|||||||
XCoreTargetLowering::LowerReturn(SDValue Chain,
|
XCoreTargetLowering::LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const {
|
DebugLoc dl, SelectionDAG &DAG) const {
|
||||||
|
|
||||||
// CCValAssign - represent the assignment of
|
// CCValAssign - represent the assignment of
|
||||||
@ -1175,7 +1178,7 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
||||||
Outs[i].Val, Flag);
|
OutVals[i], Flag);
|
||||||
|
|
||||||
// guarantee that all emitted copies are
|
// guarantee that all emitted copies are
|
||||||
// stuck together, avoiding something bad
|
// stuck together, avoiding something bad
|
||||||
|
@ -120,6 +120,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool isTailCall,
|
bool isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -178,6 +179,7 @@ namespace llvm {
|
|||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
bool &isTailCall,
|
bool &isTailCall,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const;
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
@ -186,6 +188,7 @@ namespace llvm {
|
|||||||
LowerReturn(SDValue Chain,
|
LowerReturn(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
|
const SmallVectorImpl<SDValue> &OutVals,
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
virtual bool
|
virtual bool
|
||||||
|
Loading…
Reference in New Issue
Block a user