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ARM: Let the assembler reject v5 instructions in v4 mode.

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PR18524.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199559 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2014-01-18 19:03:19 +00:00
parent ee760949ab
commit c975958498
2 changed files with 10 additions and 1 deletions
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3
lib/Target/ARM/ARMInstrInfo.td
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@ -186,7 +186,8 @@ def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
def HasV4T : Predicate<"Subtarget->hasV4TOps()">, def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
AssemblerPredicate<"HasV4TOps", "armv4t">; AssemblerPredicate<"HasV4TOps", "armv4t">;
def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
def HasV5T : Predicate<"Subtarget->hasV5TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
AssemblerPredicate<"HasV5TOps", "armv5t">;
def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
AssemblerPredicate<"HasV5TEOps", "armv5te">; AssemblerPredicate<"HasV5TEOps", "armv5te">;
def HasV6 : Predicate<"Subtarget->hasV6Ops()">, def HasV6 : Predicate<"Subtarget->hasV6Ops()">,

8
test/MC/ARM/not-armv4.s Normal file
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@ -0,0 +1,8 @@
@ RUN: not llvm-mc < %s -triple armv4-unknown-unknown -show-encoding 2>&1 | FileCheck %s
@ PR18524
@ CHECK: error: instruction requires: armv5t
clz r4,r9
@ CHECK: error: instruction requires: armv6t2
rbit r4,r9