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Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.

Browse Source 
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2012-04-02 08:32:38 +00:00
parent fab3f7ee6f
commit c97ef618d2
14 changed files with 3 additions and 31 deletions
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2
include/llvm/MC/MCInstPrinter.h
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@ -52,7 +52,7 @@ public:
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
virtual StringRef getOpcodeName(unsigned Opcode) const;
StringRef getOpcodeName(unsigned Opcode) const;
/// printRegName - Print the assembler register name.
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;

3
lib/MC/MCInstPrinter.cpp
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@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/ErrorHandling.h"
@ -20,7 +21,7 @@ MCInstPrinter::~MCInstPrinter() {
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
return "";
return MII.getName(Opcode);
}
void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {

4
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@ -44,10 +44,6 @@ ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
setAvailableFeatures(STI.getFeatureBits());
}
StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}

1
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -27,7 +27,6 @@ public:
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
// Autogenerated by tblgen.

4
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
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@ -62,10 +62,6 @@ const char* Mips::MipsFCCToString(Mips::CondCode CC) {
llvm_unreachable("Impossible condition code!");
}
StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << '$' << StringRef(getRegisterName(RegNo)).lower();
}

1
lib/Target/Mips/InstPrinter/MipsInstPrinter.h
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@ -85,7 +85,6 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);

4
lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp
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@ -36,10 +36,6 @@ PTXInstPrinter::PTXInstPrinter(const MCAsmInfo &MAI,
setAvailableFeatures(STI.getFeatureBits());
}
StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
// Decode the register number into type and offset
unsigned RegSpace = RegNo & 0x7;

1
lib/Target/PTX/InstPrinter/PTXInstPrinter.h
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@ -27,7 +27,6 @@ public:
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
// Autogenerated by tblgen.

4
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
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@ -23,10 +23,6 @@ using namespace llvm;
#include "PPCGenAsmWriter.inc"
StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}

1
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
View File

@ -34,7 +34,6 @@ public:
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

4
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
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@ -50,10 +50,6 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
raw_ostream &O) {
switch (MI->getOperand(Op).getImm()) {

1
lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
View File

@ -28,7 +28,6 @@ public:
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen, returns true if we successfully printed an
// alias.

3
lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
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@ -41,9 +41,6 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
if (CommentStream)
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
}
StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
return MII.getName(Opcode);
}
void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
raw_ostream &O) {

1
lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
View File

@ -29,7 +29,6 @@ public:
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);