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Add some methods for inline asm support.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25950 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-04 02:12:09 +00:00
parent 8666249ad6
commit c991cf58aa
1 changed files with 16 additions and 3 deletions
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19
include/llvm/Target/TargetLowering.h
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@ -298,7 +298,7 @@ public:
/// New, such that callers of SetBitsAreZero may call CombineTo on them if
/// desired.
bool DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask, SDOperand &Old,
SDOperand &New, SelectionDAG &DAG);
SDOperand &New, SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
// TargetLowering Configuration Methods - These methods should be invoked by
@ -442,13 +442,26 @@ public:
// Inline Asm Support hooks
//
enum ConstraintType {
C_RegisterClass, // Constraint represents one or more registers.
C_Other, // Something else.
C_Unknown // Unsupported constraint.
// INTEGER, ADDRESS, MEMORY?
};
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
ConstraintType getConstraintType(char ConstraintLetter) const;
/// getRegForInlineAsmConstraint - Given a constraint letter or register
/// name (e.g. "r" or "edx"), return a list of registers that can be used to
/// satisfy the constraint. If the constraint isn't supported, or isn't a
/// register constraint, return an empty list.
/// satisfy the constraint. This should only be used for physregs and
/// C_RegisterClass constraints.
virtual std::vector<unsigned>
getRegForInlineAsmConstraint(const std::string &Constraint) const;
virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
//===--------------------------------------------------------------------===//
// Scheduler hooks
//