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Don't set neverHasSideEffects on x86's divide instructions, since
they trap on divide-by-zero, and this side effect is otherwise unmodeled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59551 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -474,7 +474,6 @@ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
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} // Defs = [EFLAGS]
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} // Defs = [EFLAGS]
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// Unsigned division / remainder
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// Unsigned division / remainder
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let neverHasSideEffects = 1 in {
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
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def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
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def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
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"div{q}\t$src", []>;
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"div{q}\t$src", []>;
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@ -488,7 +487,6 @@ def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64]
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"idiv{q}\t$src", []>;
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"idiv{q}\t$src", []>;
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}
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}
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}
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}
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}
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// Unary instructions
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// Unary instructions
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let Defs = [EFLAGS], CodeSize = 2 in {
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let Defs = [EFLAGS], CodeSize = 2 in {
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@ -747,6 +747,7 @@ let Defs = [EAX,EDX], Uses = [EAX] in
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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"imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
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"imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
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}
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}
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} // neverHasSideEffects
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// unsigned division/remainder
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// unsigned division/remainder
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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@ -791,7 +792,6 @@ let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
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def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
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"idiv{l}\t$src", []>;
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"idiv{l}\t$src", []>;
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}
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}
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Two address Instructions.
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// Two address Instructions.
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