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Thumb2 PC-relative loads require a fixup rather than just an immediate.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-03-18 17:42:55 +00:00
parent d4336e29a4
commit c9bd496aa2
2 changed files with 8 additions and 1 deletions
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8
lib/Target/ARM/ARMInstrThumb2.td
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@ -95,6 +95,12 @@ def t2addrmode_imm12 : Operand<i32>,
let ParserMatchClass = MemMode5AsmOperand; let ParserMatchClass = MemMode5AsmOperand;
} }
// t2ldrlabel := imm12
def t2ldrlabel : Operand<i32> {
let EncoderMethod = "getAddrModeImm12OpValue";
}
// ADR instruction labels. // ADR instruction labels.
def t2adrlabel : Operand<i32> { def t2adrlabel : Operand<i32> {
let EncoderMethod = "getT2AdrLabelOpValue"; let EncoderMethod = "getT2AdrLabelOpValue";
@ -877,7 +883,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
} }
// FIXME: Is the pci variant actually needed? // FIXME: Is the pci variant actually needed?
def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii, def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
opc, ".w\t$Rt, $addr", opc, ".w\t$Rt, $addr",
[(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
let isReMaterializable = 1; let isReMaterializable = 1;

1
utils/TableGen/EDEmitter.cpp
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@ -602,6 +602,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("shr_imm16"); IMM("shr_imm16");
IMM("shr_imm32"); IMM("shr_imm32");
IMM("shr_imm64"); IMM("shr_imm64");
IMM("t2ldrlabel");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?