From c9bf74fdc543c2da90f334e0bf8e34b128c8a615 Mon Sep 17 00:00:00 2001
From: Venkatraman Govindaraju <venkatra@cs.wisc.edu>
Date: Sat, 1 Mar 2014 01:04:26 +0000
Subject: [PATCH] [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'.
 This improves the readability of the generated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202563 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp | 8 ++++++++
 lib/Target/Sparc/SparcInstrAliases.td             | 3 +++
 test/CodeGen/SPARC/2011-01-11-FrameAddr.ll        | 3 ++-
 test/CodeGen/SPARC/2011-01-19-DelaySlot.ll        | 6 ++++--
 test/MC/Disassembler/Sparc/sparc.txt              | 3 +++
 test/MC/Sparc/sparc-alu-instructions.s            | 3 +++
 6 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
index 0e44b31ae38..239d4ef9958 100644
--- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
+++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
@@ -20,6 +20,14 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
+// namespace. But SPARC backend uses "SP" as its namespace.
+namespace llvm {
+namespace Sparc {
+  using namespace SP;
+}
+}
+
 #define GET_INSTRUCTION_NAME
 #define PRINT_ALIAS_INSTR
 #include "SparcGenAsmWriter.inc"
diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td
index 7242c59059a..efa79243847 100644
--- a/lib/Target/Sparc/SparcInstrAliases.td
+++ b/lib/Target/Sparc/SparcInstrAliases.td
@@ -140,3 +140,6 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
 
 // mov simm13, rd -> or %g0, simm13, rd
 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
+
+// restore -> restore %g0, %g0, %g0
+def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index 95f1684d688..050b76d514d 100644
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -21,7 +21,8 @@ entry:
 ;SPARC64:       save %sp, -128, %sp
 ;SPARC64:       add  %fp, 2047, %i0
 ;SPARC64:       ret
-;SPARC64:       restore %g0, %g0, %g0
+;SPARC64-NOT:   restore %g0, %g0, %g0
+;SPARC64:       restore
 
   %0 = tail call i8* @llvm.frameaddress(i32 0)
   ret i8* %0
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 8173d6da931..60bdf06dfd0 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -141,7 +141,8 @@ entry:
 ;CHECK-LABEL:  restore_or_imm:
 ;CHECK:  or %o0, 20, %i0
 ;CHECK:  ret
-;CHECK:  restore %g0, %g0, %g0
+;CHECK-NOT:  restore %g0, %g0, %g0
+;CHECK:  restore
   %0 = tail call i32 @bar(i32 %a) nounwind
   %1 = or i32 %0, 20
   ret i32 %1
@@ -174,7 +175,8 @@ define i32 @restore_sethi_large(i32 %a) {
 entry:
 ;CHECK-LABEL: restore_sethi_large:
 ;CHECK: sethi  4000, %i0
-;CHECK: restore %g0, %g0, %g0
+;CHECK-NOT: restore %g0, %g0, %g0
+;CHECK:     restore
   %0 = tail call i32 @bar(i32 %a) nounwind
   %1 = icmp ne i32 %0, 0
   %2 = select i1 %1, i32 4096000, i32 0
diff --git a/test/MC/Disassembler/Sparc/sparc.txt b/test/MC/Disassembler/Sparc/sparc.txt
index 388dd68717e..fefde2c7038 100644
--- a/test/MC/Disassembler/Sparc/sparc.txt
+++ b/test/MC/Disassembler/Sparc/sparc.txt
@@ -167,3 +167,6 @@
 
 # CHECK: fbo 4194303
 0x1f 0xbf 0xff 0xff
+
+# CHECK: restore
+0x81 0xe8 0x00 0x00
diff --git a/test/MC/Sparc/sparc-alu-instructions.s b/test/MC/Sparc/sparc-alu-instructions.s
index 5531bcca7af..ef337b00329 100644
--- a/test/MC/Sparc/sparc-alu-instructions.s
+++ b/test/MC/Sparc/sparc-alu-instructions.s
@@ -75,3 +75,6 @@
 
         ! CHECK: or %g0, 255, %g3     ! encoding: [0x86,0x10,0x20,0xff]
         mov 0xff, %g3
+
+        ! CHECK: restore              ! encoding: [0x81,0xe8,0x00,0x00]
+        restore %g0, %g0, %g0