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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
[X86] Updates to X86 backend for f16 promotion
Summary: r235215 adds support for f16 to be considered as a load/store type and promote f16 operations to f32. This patch has miscellaneous fixes for the X86 backend so all f16 operations are handled: 1. Set loadextaction for f16 vectors to expand. 2. Handle FP_EXTEND in a switch statement when handling v2f32 3. Do not fold (FP_TO_SINT (load f16)) into FP_TO_INT*_IN_MEM or (store (SINT_TO_FP )) to a FILD. Tests included. Reviewers: ab, srhines, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pirama Arumuga Nainar
parent
2605531fe8
commit
c9f2596abc
@ -750,6 +750,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// them legal.
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if (VT.getVectorElementType() == MVT::i1)
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setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
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// EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
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// split/scalarized right now.
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if (VT.getVectorElementType() == MVT::f16)
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setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
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}
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}
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@ -17623,6 +17628,11 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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}
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case ISD::FP_TO_SINT:
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// FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
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// (FP_TO_SINT (load f16)) to FP_TO_INT*.
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if (N->getOperand(0).getValueType() == MVT::f16)
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break;
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// fallthrough
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case ISD::FP_TO_UINT: {
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bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
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@ -17668,6 +17678,13 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(V);
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return;
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}
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case ISD::FP_EXTEND: {
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// Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
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// No other ValueType for FP_EXTEND should reach this point.
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assert(N->getValueType(0) == MVT::v2f32 &&
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"Do not know how to legalize this Node");
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return;
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}
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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switch (IntNo) {
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@ -24021,6 +24038,11 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
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if (Op0.getOpcode() == ISD::LOAD) {
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LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
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EVT VT = Ld->getValueType(0);
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// This transformation is not supported if the result type is f16
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if (N->getValueType(0) == MVT::f16)
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return SDValue();
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if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
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ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
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!Subtarget->is64Bit() && VT == MVT::i64) {
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@ -1,5 +1,7 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
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define void @test_load_store(half* %in, half* %out) {
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; CHECK-LABEL: test_load_store:
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@ -30,7 +32,7 @@ define float @test_extend32(half* %addr) {
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; CHECK-LABEL: test_extend32:
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; CHECK-LIBCALL: jmp __gnu_h2f_ieee
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; CHECK-FP16: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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@ -41,8 +43,8 @@ define double @test_extend64(half* %addr) {
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: cvtss2sd
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; CHECK-FP16: vcvtph2ps
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; CHECK-FP16: vcvtss2sd
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtss2sd
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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@ -52,7 +54,7 @@ define void @test_trunc32(float %in, half* %addr) {
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; CHECK-LABEL: test_trunc32:
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-FP16: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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%val16 = fptrunc float %in to half
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store half %val16, half* %addr
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ret void
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@ -62,8 +64,200 @@ define void @test_trunc64(double %in, half* %addr) {
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; CHECK-LABEL: test_trunc64:
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; CHECK-LIBCALL: callq __truncdfhf2
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; CHECK-FP16: callq __truncdfhf2
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; CHECK-F16C: callq __truncdfhf2
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%val16 = fptrunc double %in to half
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store half %val16, half* %addr
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ret void
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}
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define i64 @test_fptosi_i64(half* %p) #0 {
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; CHECK-LABEL: test_fptosi_i64:
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; CHECK-LIBCALL-NEXT: pushq %rax
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; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, %rax
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; CHECK-LIBCALL-NEXT: popq %rdx
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; CHECK-LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG2]], %rax
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; CHECK-F16C-NEXT: retq
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%a = load half, half* %p, align 2
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%r = fptosi half %a to i64
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ret i64 %r
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}
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define void @test_sitofp_i64(i64 %a, half* %p) #0 {
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; CHECK-LABEL: test_sitofp_i64:
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; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z]+]]
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; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
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; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, %xmm0
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; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
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; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
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; CHECK_LIBCALL-NEXT: popq [[ADDR]]
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; CHECK_LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG0:%[a-z0-9]+]], [[REG0]]
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; CHECK-F16C-NEXT: vcvtps2ph $0, [[REG0]], [[REG0]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], %eax
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; CHECK-F16C-NEXT: movw %ax, (%rsi)
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; CHECK-F16C-NEXT: retq
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%r = sitofp i64 %a to half
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store half %r, half* %p
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ret void
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}
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define i64 @test_fptoui_i64(half* %p) #0 {
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; CHECK-LABEL: test_fptoui_i64:
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; FP_TO_UINT is expanded using FP_TO_SINT
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; CHECK-LIBCALL-NEXT: pushq %rax
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; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movaps %xmm0, [[REG2:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
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; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movabsq $-9223372036854775808, [[REG4:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: xorq [[REG3]], [[REG4]]
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; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: ucomiss [[REG1]], %xmm0
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; CHECK-LIBCALL-NEXT: cmovaeq [[REG4]], [[REG5]]
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; CHECK-LIBCALL-NEXT: popq %rdx
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; CHECK-LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovss {{.[A-Z_0-9]+}}(%rip), [[REG3:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vsubss [[REG3]], [[REG2]], [[REG4:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG4]], [[REG5:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: movabsq $-9223372036854775808, [[REG6:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: xorq [[REG5]], [[REG6:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG2]], [[REG7:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vucomiss [[REG3]], [[REG2]]
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; CHECK-F16C-NEXT: cmovaeq [[REG6]], %rax
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; CHECK-F16C-NEXT: retq
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%a = load half, half* %p, align 2
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%r = fptoui half %a to i64
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ret i64 %r
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}
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define void @test_uitofp_i64(i64 %a, half* %p) #0 {
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; CHECK-LABEL: test_uitofp_i64:
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; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
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; CHECK-NEXT: movl %edi, [[REG0:%[a-z0-9]+]]
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; CHECK-NEXT: andl $1, [[REG0]]
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: js [[LABEL1:.LBB[0-9_]+]]
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; simple conversion to float if non-negative
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; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]], [[REG1]]
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; CHECK-NEXT: jmp [[LABEL2:.LBB[0-9_]+]]
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; convert using shift+or if negative
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; CHECK-NEXT: [[LABEL1]]:
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; CHECK-NEXT: shrq %rdi
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; CHECK-NEXT: orq %rdi, [[REG2:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
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; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]
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; CHECK-F16C-NEXT: vaddss [[REG3]], [[REG3]], [[REG1:[%a-z0-9]+]]
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; convert float to half
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; CHECK-NEXT: [[LABEL2]]:
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; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
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; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
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; CHECK-LIBCALL-NEXT: popq [[ADDR]]
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; CHECK-F16C-NEXT: vcvtps2ph $0, [[REG1]], [[REG4:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG4]], %eax
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; CHECK-F16C-NEXT: movw %ax, (%rsi)
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; CHECK-NEXT: retq
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%r = uitofp i64 %a to half
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store half %r, half* %p
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ret void
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}
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define <4 x float> @test_extend32_vec4(<4 x half>* %p) #0 {
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; CHECK-LABEL: test_extend32_vec4:
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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%a = load <4 x half>, <4 x half>* %p, align 8
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%b = fpext <4 x half> %a to <4 x float>
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ret <4 x float> %b
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}
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define <4 x double> @test_extend64_vec4(<4 x half>* %p) #0 {
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; CHECK-LABEL: test_extend64_vec4
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL: cvtss2sd
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C: vcvtss2sd
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%a = load <4 x half>, <4 x half>* %p, align 8
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%b = fpext <4 x half> %a to <4 x double>
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ret <4 x double> %b
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}
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define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) {
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; CHECK-LABEL: test_trunc32_vec4:
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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%v = fptrunc <4 x float> %a to <4 x half>
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store <4 x half> %v, <4 x half>* %p
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ret void
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}
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define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) {
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; CHECK-LABEL: test_trunc64_vec4:
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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%v = fptrunc <4 x double> %a to <4 x half>
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store <4 x half> %v, <4 x half>* %p
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ret void
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}
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attributes #0 = { nounwind }
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