Change target-specific classes to use more precise static types.

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.h

@@ -134,7 +134,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.

lib/Target/ARM/ARMTargetMachine.h

@@ -38,10 +38,10 @@ class ARMTargetMachine : public LLVMTargetMachine {
 public:
   ARMTargetMachine(const Module &M, const std::string &FS, bool isThumb = false);
 
-  virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
+  virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
-  virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
+  virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
-  virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
+  virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  virtual const ARMRegisterInfo  *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }

lib/Target/Alpha/Alpha.h

@@ -25,7 +25,7 @@ namespace llvm {
   class MachineCodeEmitter;
 
   FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
-  FunctionPass *createAlphaISelDag(TargetMachine &TM);
+  FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
                                              TargetMachine &TM);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);

lib/Target/Alpha/AlphaISelDAGToDAG.cpp

@@ -146,9 +146,9 @@ namespace {
     }
 
   public:
-    AlphaDAGToDAGISel(TargetMachine &TM)
+    explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
       : SelectionDAGISel(AlphaLowering), 
-        AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) 
+        AlphaLowering(*TM.getTargetLowering())
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
@@ -559,6 +559,6 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
 /// createAlphaISelDag - This pass converts a legalized DAG into a 
 /// Alpha-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
   return new AlphaDAGToDAGISel(TM);
 }

lib/Target/Alpha/AlphaInstrInfo.h

@@ -28,7 +28,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// Return true if the instruction is a register to register move and
   /// leave the source and dest operands in the passed parameters.

lib/Target/Alpha/AlphaTargetMachine.h

@@ -42,15 +42,15 @@ public:
 
   virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
-  virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
+  virtual const AlphaSubtarget   *getSubtargetImpl() const{ return &Subtarget; }
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  virtual const AlphaRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
-  virtual TargetLowering* getTargetLowering() const { 
+  virtual AlphaTargetLowering* getTargetLowering() const { 
     return const_cast<AlphaTargetLowering*>(&TLInfo);
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
-  virtual TargetJITInfo* getJITInfo() {
+  virtual AlphaJITInfo* getJITInfo() {
     return &JITInfo;
   }
 

lib/Target/CellSPU/SPUInstrInfo.h

@@ -30,7 +30,7 @@ namespace llvm {
     /// such, whenever a client has an instance of instruction info, it should
     /// always be able to get register info as well (through this method).
     ///
-    virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+    virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
 
     /// getPointerRegClass - Return the register class to use to hold pointers.
     /// This is used for addressing modes.

lib/Target/CellSPU/SPUTargetMachine.h

@@ -49,7 +49,7 @@ public:
   virtual const SPUInstrInfo     *getInstrInfo() const {
     return &InstrInfo;
   }
-  virtual const TargetFrameInfo  *getFrameInfo() const {
+  virtual const SPUFrameInfo     *getFrameInfo() const {
     return &FrameInfo;
   }
   /*!
@@ -70,7 +70,7 @@ public:
    return const_cast<SPUTargetLowering*>(&TLInfo); 
   }
 
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  virtual const SPURegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   

lib/Target/IA64/IA64InstrInfo.h

@@ -28,7 +28,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const IA64RegisterInfo &getRegisterInfo() const { return RI; }
 
   //
   // Return true if the instruction is a register to register move and

lib/Target/IA64/IA64TargetMachine.h

@@ -40,7 +40,7 @@ public:
   virtual       IA64TargetLowering *getTargetLowering() const { 
     return const_cast<IA64TargetLowering*>(&TLInfo);
   }
-  virtual const TargetRegisterInfo    *getRegisterInfo() const {
+  virtual const IA64RegisterInfo   *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }

lib/Target/Mips/MipsInstrInfo.h

@@ -52,7 +52,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// Return true if the instruction is a register to register move and
   /// leave the source and dest operands in the passed parameters.

lib/Target/Mips/MipsTargetMachine.h

@@ -39,12 +39,12 @@ namespace llvm {
     { return &InstrInfo; }
     virtual const TargetFrameInfo *getFrameInfo()     const 
     { return &FrameInfo; }
-    virtual const TargetSubtarget *getSubtargetImpl() const 
+    virtual const MipsSubtarget   *getSubtargetImpl() const 
     { return &Subtarget; }
     virtual const TargetData      *getTargetData()    const 
     { return &DataLayout;}
 
-    virtual const TargetRegisterInfo   *getRegisterInfo()  const {
+    virtual const MipsRegisterInfo *getRegisterInfo()  const {
       return &InstrInfo.getRegisterInfo();
     }
 

lib/Target/PIC16/PIC16InstrInfo.h

@@ -32,7 +32,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const PIC16RegisterInfo &getRegisterInfo() const { return RI; }
 
   
   /// isLoadFromStackSlot - If the specified machine instruction is a direct

lib/Target/PIC16/PIC16TargetMachine.h

@@ -47,7 +47,7 @@ public:
   { return &DataLayout; }
   virtual PIC16TargetLowering *getTargetLowering() const 
   { return const_cast<PIC16TargetLowering*>(&TLInfo); }
-  virtual const TargetRegisterInfo *getRegisterInfo() const 
+  virtual const PIC16RegisterInfo *getRegisterInfo() const 
   { return &InstrInfo.getRegisterInfo(); }
   
   virtual bool addInstSelector(PassManagerBase &PM, bool Fast);

lib/Target/PowerPC/PPCInstrInfo.h

@@ -78,7 +78,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.

lib/Target/PowerPC/PPCTargetMachine.h

@@ -46,12 +46,12 @@ public:
   PPCTargetMachine(const Module &M, const std::string &FS, bool is64Bit);
 
   virtual const PPCInstrInfo     *getInstrInfo() const { return &InstrInfo; }
-  virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
+  virtual const PPCFrameInfo     *getFrameInfo() const { return &FrameInfo; }
-  virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
+  virtual       PPCJITInfo       *getJITInfo()         { return &JITInfo; }
   virtual       PPCTargetLowering *getTargetLowering() const { 
    return const_cast<PPCTargetLowering*>(&TLInfo); 
   }
-  virtual const TargetRegisterInfo    *getRegisterInfo() const {
+  virtual const PPCRegisterInfo  *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   

lib/Target/Sparc/SparcInstrInfo.h

@@ -41,7 +41,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
 
   /// Return true if the instruction is a register to register move and
   /// leave the source and dest operands in the passed parameters.

lib/Target/Sparc/SparcTargetMachine.h

@@ -38,8 +38,8 @@ public:
 
   virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
-  virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
+  virtual const SparcSubtarget   *getSubtargetImpl() const{ return &Subtarget; }
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  virtual const SparcRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }

lib/Target/X86/X86CodeEmitter.cpp

@@ -38,18 +38,18 @@ namespace {
   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
     const X86InstrInfo  *II;
     const TargetData    *TD;
-    TargetMachine       &TM;
+    X86TargetMachine    &TM;
     MachineCodeEmitter  &MCE;
     intptr_t PICBaseOffset;
     bool Is64BitMode;
     bool IsPIC;
   public:
     static char ID;
-    explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
+    explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
       : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm), 
       MCE(mce), PICBaseOffset(0), Is64BitMode(false),
       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
-    Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
+    Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
             const X86InstrInfo &ii, const TargetData &td, bool is64)
       : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm), 
       MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
@@ -112,8 +112,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
   
   MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
   
-  II = ((X86TargetMachine&)TM).getInstrInfo();
+  II = TM.getInstrInfo();
-  TD = ((X86TargetMachine&)TM).getTargetData();
+  TD = TM.getTargetData();
   Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
   
   do {
@@ -220,7 +220,7 @@ void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
 }
 
 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
-  return ((const X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
+  return II->getRegisterInfo().getX86RegNum(RegNo);
 }
 
 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
@@ -503,7 +503,7 @@ void Emitter::emitInstruction(const MachineInstr &MI,
       emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
       // Remember PIC base.
       PICBaseOffset = MCE.getCurrentPCOffset();
-      X86JITInfo *JTI = dynamic_cast<X86JITInfo*>(TM.getJITInfo());
+      X86JITInfo *JTI = TM.getJITInfo();
       JTI->setPICBase(MCE.getCurrentPCValue());
       break;
     }

lib/Target/X86/X86ISelLowering.cpp

@@ -44,7 +44,7 @@ using namespace llvm;
 // Forward declarations.
 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
 
-X86TargetLowering::X86TargetLowering(TargetMachine &TM)
+X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
   : TargetLowering(TM) {
   Subtarget = &TM.getSubtarget<X86Subtarget>();
   X86ScalarSSEf64 = Subtarget->hasSSE2();
@@ -5284,10 +5284,8 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
     const unsigned char JMP64r  = TII->getBaseOpcodeFor(X86::JMP64r);
     const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
 
-    const unsigned char N86R10 =
+    const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
-      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
+    const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
-    const unsigned char N86R11 =
-      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
 
     const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
 
@@ -5374,8 +5372,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
     Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
 
     const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
-    const unsigned char N86Reg =
+    const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
-      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
     OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
                                 Trmp, TrmpAddr, 0);
 

lib/Target/X86/X86ISelLowering.h

@@ -311,7 +311,7 @@ namespace llvm {
     int BytesCallerReserves;          // Number of arg bytes caller makes.
 
   public:
-    explicit X86TargetLowering(TargetMachine &TM);
+    explicit X86TargetLowering(X86TargetMachine &TM);
 
     /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
     /// jumptable.
@@ -454,7 +454,7 @@ namespace llvm {
     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
     /// make the right decision when generating code for different targets.
     const X86Subtarget *Subtarget;
-    const TargetRegisterInfo *RegInfo;
+    const X86RegisterInfo *RegInfo;
 
     /// X86StackPtr - X86 physical register used as stack ptr.
     unsigned X86StackPtr;

lib/Target/X86/X86InstrInfo.cpp

@@ -2820,7 +2820,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
   const TargetInstrDesc &Desc = MI->getDesc();
   bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
-  bool Is64BitMode = ((X86Subtarget*)TM.getSubtargetImpl())->is64Bit();
+  bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
   unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
   if (Desc.getOpcode() == X86::MOVPC32r) {
     Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);

lib/Target/X86/X86InstrInfo.h

@@ -250,7 +250,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
 
   // Return true if the instruction is a register to register move and
   // leave the source and dest operands in the passed parameters.

lib/Target/X86/X86TargetMachine.h

@@ -44,12 +44,12 @@ public:
 
   virtual const X86InstrInfo     *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
-  virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
+  virtual       X86JITInfo       *getJITInfo()         { return &JITInfo; }
-  virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
+  virtual const X86Subtarget     *getSubtargetImpl() const{ return &Subtarget; }
   virtual       X86TargetLowering *getTargetLowering() const { 
     return const_cast<X86TargetLowering*>(&TLInfo); 
   }
-  virtual const TargetRegisterInfo    *getRegisterInfo() const {
+  virtual const X86RegisterInfo  *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }