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Combine FMA4 PS/PD patterns with the instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
2e9ed29449
commit
ca28590d8b
@ -116,64 +116,86 @@ multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop> {
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[]>;
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}
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multiclass fma4p<bits<8> opc, string OpcodeStr> {
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multiclass fma4p<bits<8> opc, string OpcodeStr,
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Intrinsic Int128, Intrinsic Int256,
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PatFrag ld_frag128, PatFrag ld_frag256> {
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def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
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(ld_frag128 addr:$src3)))]>, XOP_W;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>;
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[(set VR128:$dst,
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(Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
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def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR256:$dst,
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(Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, XOP_W;
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def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_W;
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
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(ld_frag256 addr:$src3)))]>, XOP_W;
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def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>;
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[(set VR256:$dst,
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(Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
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}
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let isAsmParserOnly = 1 in {
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defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem>;
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defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem>;
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defm VFMADDPS4 : fma4p<0x68, "vfmaddps">;
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defm VFMADDPD4 : fma4p<0x69, "vfmaddpd">;
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defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
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int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
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defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
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int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
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defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem>;
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defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem>;
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defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps">;
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defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd">;
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defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
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int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
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defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
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int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
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defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem>;
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defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem>;
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defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps">;
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defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd">;
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defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
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int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
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defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
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int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
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defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem>;
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defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem>;
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defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps">;
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defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd">;
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defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps">;
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defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd">;
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defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps">;
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defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd">;
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defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
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int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
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defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
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int_x86_fma4_vfnmsub_pd_256, memopv2f64, memopv4f64>;
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defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma4_vfmaddsub_ps,
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int_x86_fma4_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
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defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma4_vfmaddsub_pd,
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int_x86_fma4_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
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defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma4_vfmsubadd_ps,
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int_x86_fma4_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
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defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
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int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;
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}
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// FMA4 Intrinsics patterns
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let Predicates = [HasFMA4] in {
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// VFMADD
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def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -189,42 +211,6 @@ def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2,
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(memopv4f32 addr:$src3)),
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(VFMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2,
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(memopv2f64 addr:$src3)),
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(VFMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, (memopv2f64 addr:$src2),
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VR128:$src3),
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(VFMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2,
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(memopv8f32 addr:$src3)),
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(VFMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, (memopv8f32 addr:$src2),
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VR256:$src3),
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(VFMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2,
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(memopv4f64 addr:$src3)),
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(VFMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, (memopv4f64 addr:$src2),
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VR256:$src3),
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(VFMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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// VFMSUB
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def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -240,42 +226,6 @@ def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
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def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2,
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(memopv4f32 addr:$src3)),
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(VFMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2,
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(memopv2f64 addr:$src3)),
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(VFMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, (memopv2f64 addr:$src2),
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VR128:$src3),
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(VFMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2,
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(memopv8f32 addr:$src3)),
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(VFMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, (memopv8f32 addr:$src2),
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VR256:$src3),
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(VFMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2,
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(memopv4f64 addr:$src3)),
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(VFMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, (memopv4f64 addr:$src2),
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VR256:$src3),
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(VFMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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// VFNMADD
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def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -291,42 +241,6 @@ def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3)
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def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2,
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(memopv4f32 addr:$src3)),
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(VFNMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFNMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2,
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(memopv2f64 addr:$src3)),
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(VFNMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, (memopv2f64 addr:$src2),
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VR128:$src3),
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(VFNMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFNMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2,
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(memopv8f32 addr:$src3)),
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(VFNMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, (memopv8f32 addr:$src2),
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VR256:$src3),
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(VFNMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
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(VFNMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2,
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(memopv4f64 addr:$src3)),
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(VFNMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, (memopv4f64 addr:$src2),
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VR256:$src3),
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(VFNMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
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// VFNMSUB
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def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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@ -342,114 +256,23 @@ def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3)
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def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
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(VFNMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2,
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(memopv4f32 addr:$src3)),
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(VFNMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, (memopv4f32 addr:$src2),
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VR128:$src3),
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(VFNMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
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(VFNMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFNMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, (memopv2f64 addr:$src2),
|
||||
VR128:$src3),
|
||||
(VFNMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFNMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFNMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1,
|
||||
(memopv8f32 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFNMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFNMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFNMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1,
|
||||
(memopv4f64 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFNMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VFMADDSUB
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VFMADDSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMADDSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, (memopv4f32 addr:$src2),
|
||||
VR128:$src3),
|
||||
(VFMADDSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VFMADDSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMADDSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, (memopv2f64 addr:$src2),
|
||||
VR128:$src3),
|
||||
(VFMADDSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFMADDSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMADDSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, (memopv8f32 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFMADDSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFMADDSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMADDSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, (memopv4f64 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFMADDSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
// VFMSUBADD
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VFMSUBADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2,
|
||||
(memopv4f32 addr:$src3)),
|
||||
(VFMSUBADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, (memopv4f32 addr:$src2),
|
||||
VR128:$src3),
|
||||
(VFMSUBADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
(VFMSUBADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2,
|
||||
(memopv2f64 addr:$src3)),
|
||||
(VFMSUBADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, (memopv2f64 addr:$src2),
|
||||
VR128:$src3),
|
||||
(VFMSUBADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFMSUBADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2,
|
||||
(memopv8f32 addr:$src3)),
|
||||
(VFMSUBADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, (memopv8f32 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFMSUBADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
(VFMSUBADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2,
|
||||
(memopv4f64 addr:$src3)),
|
||||
(VFMSUBADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
|
||||
def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, (memopv4f64 addr:$src2),
|
||||
VR256:$src3),
|
||||
(VFMSUBADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
|
||||
} // Predicates = [HasFMA4]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user