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Compute a backwards SubReg -> SubRegIndex map for each register.

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This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-09 22:15:00 +00:00
parent da2be82434
commit ca313e1efa
2 changed files with 23 additions and 0 deletions
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16
utils/TableGen/CodeGenRegisters.cpp
View File

@ -191,6 +191,9 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
" appears twice in Register " + getName());
// Map explicit sub-registers first, so the names take precedence.
// The inherited sub-registers are mapped below.
SubReg2Idx.insert(std::make_pair(SR, Idx));
}
// Keep track of inherited subregs and how they can be reached.
@ -309,6 +312,19 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
}
// Compute the inverse SubReg -> Idx map.
for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
SI != SE; ++SI) {
// Ignore idempotent sub-register indices.
if (SI->second == this)
continue;
// Is is possible to have multiple names for the same sub-register.
// For example, XMM0 appears as sub_xmm, sub_sd, and sub_ss in YMM0.
// Eventually, this degeneration should go away, but for now we simply give
// precedence to the explicit sub-register index over the inherited ones.
SubReg2Idx.insert(std::make_pair(SI->second, SI->first));
}
// Initialize RegUnitList. A register with no subregisters creates its own
// unit. Otherwise, it inherits all its subregister's units. Because
// getSubRegs is called recursively, this processes the register hierarchy in

7
utils/TableGen/CodeGenRegisters.h
View File

@ -113,6 +113,12 @@ namespace llvm {
void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
CodeGenRegBank&) const;
// Return the sub-register index naming Reg as a sub-register of this
// register. Returns NULL if Reg is not a sub-register.
CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
return SubReg2Idx.lookup(Reg);
}
// List of super-registers in topological order, small to large.
typedef std::vector<const CodeGenRegister*> SuperRegList;
@ -157,6 +163,7 @@ namespace llvm {
bool SubRegsComplete;
SubRegMap SubRegs;
SuperRegList SuperRegs;
DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
RegUnitList RegUnits;
};