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https://github.com/c64scene-ar/llvm-6502.git
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Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
8a186ae4aa
commit
ca57f78332
@ -243,6 +243,16 @@ def loadi16 : PatFrag<(ops node:$ptr), (i16 (ld node:$ptr)), [{
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return false;
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}]>;
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def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (ld node:$ptr)), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType == ISD::EXTLOAD)
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return LD->getAlignment() >= 2 && !LD->isVolatile();
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return false;
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}]>;
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def loadi32 : PatFrag<(ops node:$ptr), (i32 (ld node:$ptr)), [{
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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@ -162,6 +162,17 @@ def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
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def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
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def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
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def vzmovl_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzmovl
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(v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
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def vzmovl_v4i32 : PatFrag<(ops node:$src),
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(bitconvert (v4i32 (X86vzmovl
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(v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
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def vzload_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzload node:$src)))>;
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def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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@ -3368,8 +3379,9 @@ multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
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[(set VR128:$dst,
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(IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
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OpSize;
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}
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defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
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@ -3379,6 +3391,38 @@ defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
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defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
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defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
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// Common patterns involving scalar load.
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def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
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(PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
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(PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
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(PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
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(PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
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(PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
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(PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
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(PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
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(PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
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(PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
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(PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
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(PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
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def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
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(PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
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multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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@ -3386,8 +3430,9 @@ multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
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[(set VR128:$dst,
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(IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
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OpSize;
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}
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defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
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@ -3395,20 +3440,45 @@ defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
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defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
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defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
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// Common patterns involving scalar load
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def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
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(PMOVSXBDrm addr:$src)>;
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def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
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(PMOVSXWQrm addr:$src)>;
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def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
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(PMOVZXBDrm addr:$src)>;
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def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
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(PMOVZXWQrm addr:$src)>;
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multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
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// Expecting a i16 load any extended to i32 value.
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
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[(set VR128:$dst, (IntId (bitconvert
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(v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
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OpSize;
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}
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defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
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defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
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// Common patterns involving scalar load
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def : Pat<(int_x86_sse41_pmovsxbq
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(bitconvert (v4i32 (X86vzmovl
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(PMOVSXBQrm addr:$src)>;
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def : Pat<(int_x86_sse41_pmovzxbq
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(bitconvert (v4i32 (X86vzmovl
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(PMOVZXBQrm addr:$src)>;
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/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
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multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
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47
test/CodeGen/X86/sse41-pmovx.ll
Normal file
47
test/CodeGen/X86/sse41-pmovx.ll
Normal file
@ -0,0 +1,47 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | not grep movd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | not grep movq
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovsxbd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovsxwd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovsxbq
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; RUN: llvm-as < %s | llc -march=x86-64 -mattr=sse41 | grep movq | count 1
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define <2 x i64> @t1(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 4 ; <i32> [#uses=1]
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0 ; <<4 x i32>> [#uses=1]
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%2 = insertelement <4 x i32> %1, i32 0, i32 1 ; <<4 x i32>> [#uses=1]
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%3 = insertelement <4 x i32> %2, i32 0, i32 2 ; <<4 x i32>> [#uses=1]
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%4 = insertelement <4 x i32> %3, i32 0, i32 3 ; <<4 x i32>> [#uses=1]
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%5 = bitcast <4 x i32> %4 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone ; <<4 x i32>> [#uses=1]
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%7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %7
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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define <2 x i64> @t2(i64* %p) nounwind readonly {
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entry:
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%0 = load i64* %p ; <i64> [#uses=1]
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
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%3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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@gv = external global i16 ; <i16*> [#uses=1]
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define <2 x i64> @t3() nounwind {
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entry:
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%0 = load i16* @gv, align 2 ; <i16> [#uses=1]
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
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%2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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