6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-10-28 17:33:28 +00:00
parent cd0fee86de
commit ca5dfb71ba
5 changed files with 4 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -40,11 +40,6 @@
#include "llvm/Support/CommandLine.h"
using namespace llvm;
static cl::opt<bool>
ScavengeFrameIndexVals("arm-virtual-frame-index-vals", cl::Hidden,
cl::init(true),
cl::desc("Resolve frame index values via scavenging in PEI"));
static cl::opt<bool>
ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
cl::desc("Reuse repeated frame index values"));
@ -1022,7 +1017,7 @@ requiresRegisterScavenging(const MachineFunction &MF) const {
bool ARMBaseRegisterInfo::
requiresFrameIndexScavenging(const MachineFunction &MF) const {
return ScavengeFrameIndexVals;
return true;
}
// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
@ -1100,17 +1095,6 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MBB.erase(I);
}
/// findScratchRegister - Find a 'free' ARM register. If register scavenger
/// is not being used, R12 is available. Otherwise, try for a call-clobbered
/// register first and then a spilled callee-saved register if that fails.
static
unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
ARMFunctionInfo *AFI) {
unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
assert(!AFI->isThumb1OnlyFunction());
return Reg;
}
unsigned
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int *Value,
@ -1186,19 +1170,8 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Must be addrmode4.
MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
else {
if (!ScavengeFrameIndexVals) {
// Insert a set of r12 with the full address: r12 = sp + offset
// If the offset we have is too large to fit into the instruction, we need
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
// out of 'Offset'.
ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
if (ScratchReg == 0)
// No register is "free". Scavenge a register.
ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
} else {
ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
*Value = Offset;
}
ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
if (Value) *Value = Offset;
if (!AFI->isThumbFunction())
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
Offset, Pred, PredReg, TII);
@ -1208,7 +1181,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
Offset, Pred, PredReg, TII);
}
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
if (!ReuseFrameIndexVals || !ScavengeFrameIndexVals)
if (!ReuseFrameIndexVals)
ScratchReg = 0;
}
return ScratchReg;

12
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -76,18 +76,6 @@ Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
}
bool
Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
}
bool
Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
const {
return true;
}
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();

3
lib/Target/ARM/Thumb1RegisterInfo.h
View File

@ -40,9 +40,6 @@ public:
const TargetRegisterClass *
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
bool hasReservedCallFrame(MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,

5
lib/Target/ARM/Thumb2RegisterInfo.cpp
View File

@ -60,8 +60,3 @@ void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
.addReg(DestReg, getDefRegState(true), SubIdx)
.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0);
}
bool Thumb2RegisterInfo::
requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
}

2
lib/Target/ARM/Thumb2RegisterInfo.h
View File

@ -35,8 +35,6 @@ public:
unsigned DestReg, unsigned SubIdx, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
};
}