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merge sse41-pmovx.ll into sse41.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76850 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,48 +0,0 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | not grep movd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | not grep movq
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovsxbd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovsxwd
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pmovzxbq
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; RUN: llvm-as < %s | llc -march=x86-64 -mattr=sse41 -mtriple=x86_64-apple-darwin | grep movq | count 1
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; RUN: llvm-as < %s | llc -march=x86-64 -mattr=sse41 -mtriple=x86_64-unknown-linux-gnu | not grep movq
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define <2 x i64> @t1(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 4 ; <i32> [#uses=1]
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0 ; <<4 x i32>> [#uses=1]
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%2 = insertelement <4 x i32> %1, i32 0, i32 1 ; <<4 x i32>> [#uses=1]
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%3 = insertelement <4 x i32> %2, i32 0, i32 2 ; <<4 x i32>> [#uses=1]
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%4 = insertelement <4 x i32> %3, i32 0, i32 3 ; <<4 x i32>> [#uses=1]
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%5 = bitcast <4 x i32> %4 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone ; <<4 x i32>> [#uses=1]
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%7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %7
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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define <2 x i64> @t2(i64* %p) nounwind readonly {
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entry:
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%0 = load i64* %p ; <i64> [#uses=1]
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
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%3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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@gv = external global i16 ; <i16*> [#uses=1]
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define <2 x i64> @t3() nounwind {
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entry:
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%0 = load i16* @gv, align 2 ; <i16> [#uses=1]
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
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%2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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@ -1,23 +1,86 @@
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; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
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@g16 = external global i16
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define <4 x i32> @pinsrd(i32 %s, <4 x i32> %tmp) nounwind {
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define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
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%tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
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ret <4 x i32> %tmp1
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; X32: pinsrd:
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; X32: pinsrd_1:
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; X32: pinsrd $1, 4(%esp), %xmm0
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; X64: pinsrd:
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; X64: pinsrd_1:
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; X64: pinsrd $1, %edi, %xmm0
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}
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define <16 x i8> @pinsrb(i8 %s, <16 x i8> %tmp) nounwind {
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define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
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%tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
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ret <16 x i8> %tmp1
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; X32: pinsrb:
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; X32: pinsrb_1:
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; X32: pinsrb $1, 4(%esp), %xmm0
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; X64: pinsrb:
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; X64: pinsrb_1:
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; X64: pinsrb $1, %edi, %xmm0
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}
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define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 4
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0
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%2 = insertelement <4 x i32> %1, i32 0, i32 1
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%3 = insertelement <4 x i32> %2, i32 0, i32 2
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%4 = insertelement <4 x i32> %3, i32 0, i32 3
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%5 = bitcast <4 x i32> %4 to <16 x i8>
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%6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
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%7 = bitcast <4 x i32> %6 to <2 x i64>
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ret <2 x i64> %7
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; X32: _pmovsxbd_1:
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; X32: movl 4(%esp), %eax
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; X32: pmovsxbd (%eax), %xmm0
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; X64: _pmovsxbd_1:
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; X64: pmovsxbd (%rdi), %xmm0
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}
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define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
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entry:
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%0 = load i64* %p ; <i64> [#uses=1]
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
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%3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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; X32: _pmovsxwd_1:
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; X32: movl 4(%esp), %eax
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; X32: pmovsxwd (%eax), %xmm0
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; X64: _pmovsxwd_1:
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; X64: pmovsxwd (%rdi), %xmm0
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}
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define <2 x i64> @pmovzxbq_1() nounwind {
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entry:
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%0 = load i16* @g16, align 2 ; <i16> [#uses=1]
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
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%2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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; X32: _pmovzxbq_1:
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; X32: movl L_g16$non_lazy_ptr, %eax
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; X32: pmovzxbq (%eax), %xmm0
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; X64: _pmovzxbq_1:
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; X64: movq _g16@GOTPCREL(%rip), %rax
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; X64: pmovzxbq (%rax), %xmm0
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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