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Fix computation of # operands, add a temporary hack for CopyToReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22896 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -73,11 +73,16 @@ unsigned SimpleSched::Emit(SDOperand Op) {
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// Target nodes have any register or immediate operands before any chain
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// Target nodes have any register or immediate operands before any chain
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// nodes. Check that the DAG matches the TD files's expectation of #
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// nodes. Check that the DAG matches the TD files's expectation of #
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// operands.
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// operands.
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assert((unsigned(II.numOperands) == Op.getNumOperands() ||
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#ifndef _NDEBUG
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// It could be some number of operands followed by a token chain.
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unsigned Operands = Op.getNumOperands();
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(unsigned(II.numOperands)+1 == Op.getNumOperands() &&
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if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
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Op.getOperand(II.numOperands).getValueType() == MVT::Other)) &&
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--Operands;
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unsigned Results = Op.Val->getNumValues();
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if (Results && Op.getOperand(Results-1).getValueType() == MVT::Other)
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--Results;
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assert(unsigned(II.numOperands) == Operands+Results &&
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"#operands for dag node doesn't match .td file!");
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
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MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
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@ -107,9 +112,15 @@ unsigned SimpleSched::Emit(SDOperand Op) {
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BB->insert(BB->end(), MI);
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BB->insert(BB->end(), MI);
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} else {
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} else {
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switch (Op.getOpcode()) {
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switch (Op.getOpcode()) {
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default: assert(0 &&
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default:
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"This target-independent node should have been selected!");
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Op.Val->dump();
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: break;
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case ISD::EntryToken: break;
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case ISD::CopyToReg: {
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unsigned Val = Emit(Op.getOperand(2));
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// FIXME: DO THE COPY NOW.
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break;
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}
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}
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}
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}
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}
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