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Fix typos in my prev commit, found by Tobi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13445,7 +13445,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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ISD::LoadExtType Ext = Ld->getExtensionType();
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// If yhis is a vector EXT Load then attempt to optimize it using a
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// If this is a vector EXT Load then attempt to optimize it using a
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// shuffle. We need SSE4 for the shuffles.
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// TODO: It is possible to support ZExt by zeroing the undef values
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// during the shuffle phase or after the shuffle.
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@ -13457,7 +13457,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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unsigned RegSz = RegVT.getSizeInBits();
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unsigned MemSz = MemVT.getSizeInBits();
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assert(RegSz > MemSz && "Register size must be greater than the mem size");
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// All sized must be a power of two
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// All sizes must be a power of two
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if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
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// Attempt to load the original value using a single load op.
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