6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-15 22:28:18 +00:00
Code Issues Projects Releases Wiki Activity

[X86] Be more robust against unknown Intel family 6 models. Use feature flags to guess what it might be.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233671 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2015-03-31 05:42:45 +00:00
parent 18128bd376
commit caa12e0352
1 changed files with 42 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
lib/Support/Host.cpp
View File

@@ -225,20 +225,30 @@ StringRef sys::getHostCPUName() {
char c[12]; char c[12];
} text; } text;
GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1); unsigned MaxLeaf;
GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1);
unsigned MaxLeaf = EAX; bool HasMMX = (EDX >> 23) & 1;
bool HasSSE3 = (ECX & 0x1); bool HasSSE = (EDX >> 25) & 1;
bool HasSSE41 = (ECX & 0x80000); bool HasSSE2 = (EDX >> 26) & 1;
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV bool HasSSE3 = (ECX >> 0) & 1;
bool HasSSSE3 = (ECX >> 9) & 1;
bool HasSSE41 = (ECX >> 19) & 1;
bool HasSSE42 = (ECX >> 20) & 1;
bool HasMOVBE = (ECX >> 22) & 1;
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context // indicates that the AVX registers will be saved and restored on context
// switch, then we have full AVX support. // switch, then we have full AVX support.
const unsigned AVXBits = (1 << 27) | (1 << 28); const unsigned AVXBits = (1 << 27) | (1 << 28);
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) && bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
((EAX & 0x6) == 0x6); ((EAX & 0x6) == 0x6);
bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 && bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) && bool HasLeaf7 = MaxLeaf >= 0x7 &&
(EBX & 0x20); !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1; bool Em64T = (EDX >> 29) & 0x1;
bool HasTBM = (ECX >> 21) & 0x1; bool HasTBM = (ECX >> 21) & 0x1;
@@ -382,7 +392,30 @@ StringRef sys::getHostCPUName() {
case 77: case 77:
return "silvermont"; return "silvermont";
default: return (Em64T) ? "x86-64" : "i686"; default: // Unknown family 6 CPU, try to guess.
if (HasAVX512)
return "knl";
if (HasADX)
return "broadwell";
if (HasAVX2)
return "haswell";
if (HasAVX)
return "sandybridge";
if (HasSSE42)
return HasMOVBE ? "silvermont" : "nehalem";
if (HasSSE41)
return "penryn";
if (HasSSSE3)
return HasMOVBE ? "bonnell" : "core2";
if (Em64T)
return "x86-64";
if (HasSSE2)
return "pentium-m";
if (HasSSE)
return "pentium3";
if (HasMMX)
return "pentium2";
return "pentiumpro";
} }
case 15: { case 15: {
switch (Model) { switch (Model) {