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Add support for matching vmrg(x,x) patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27463 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -293,9 +293,10 @@ bool PPC::isVPKUWUMShuffleMask(SDNode *N) {
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return true;
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}
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) {
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/// isVMerge - Common function, used to match vmrg* shuffles.
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///
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static bool isVMerge(SDNode *N, unsigned UnitSize,
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unsigned LHSStart, unsigned RHSStart) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR &&
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N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
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assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
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@ -304,31 +305,28 @@ bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) {
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for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
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for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
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if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
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8+j+i*UnitSize) ||
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LHSStart+j+i*UnitSize) ||
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!isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
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24+j+i*UnitSize))
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RHSStart+j+i*UnitSize))
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return false;
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}
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return true;
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}
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
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if (!isUnary)
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return isVMerge(N, UnitSize, 8, 24);
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return isVMerge(N, UnitSize, 8, 8);
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}
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR &&
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N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
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assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
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"Unsupported merge size!");
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for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
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for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
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if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
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0+j+i*UnitSize) ||
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!isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
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16+j+i*UnitSize))
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return false;
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}
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return true;
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bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
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if (!isUnary)
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return isVMerge(N, UnitSize, 0, 16);
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return isVMerge(N, UnitSize, 0, 0);
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}
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@ -870,22 +868,30 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Cases that are handled by instructions that take permute immediates
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// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
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// selected by the instruction selector.
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if (V2.getOpcode() == ISD::UNDEF &&
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(PPC::isSplatShuffleMask(PermMask.Val, 1) ||
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if (V2.getOpcode() == ISD::UNDEF) {
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if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
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PPC::isSplatShuffleMask(PermMask.Val, 2) ||
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PPC::isSplatShuffleMask(PermMask.Val, 4) ||
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PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1))
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PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
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return Op;
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}
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}
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if (PPC::isVPKUWUMShuffleMask(PermMask.Val) ||
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PPC::isVPKUHUMShuffleMask(PermMask.Val) ||
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PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4))
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
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return Op;
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// TODO: Handle more cases, and also handle cases that are cheaper to do as
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@ -112,11 +112,11 @@ namespace llvm {
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize);
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bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize);
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bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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@ -25,22 +25,41 @@ def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
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}]>;
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def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 1);
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return PPC::isVMRGLShuffleMask(N, 1, false);
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}]>;
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def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 2);
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return PPC::isVMRGLShuffleMask(N, 2, false);
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}]>;
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def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 4);
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return PPC::isVMRGLShuffleMask(N, 4, false);
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}]>;
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def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 1);
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return PPC::isVMRGHShuffleMask(N, 1, false);
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}]>;
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def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 2);
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return PPC::isVMRGHShuffleMask(N, 2, false);
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}]>;
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def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 4);
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return PPC::isVMRGHShuffleMask(N, 4, false);
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}]>;
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def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 1, true);
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}]>;
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def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 2, true);
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}]>;
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def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 4, true);
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}]>;
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def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 1, true);
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}]>;
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def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 2, true);
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}]>;
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def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 4, true);
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}]>;
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@ -566,6 +585,21 @@ def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA),undef, VSLDOI_rotate_shuffle_mask:$in),
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(VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_rotate_shuffle_mask:$in)>;
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// Match vmrg*(x,x)
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
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(VMRGLB VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
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(VMRGLH VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
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(VMRGLW VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
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(VMRGHB VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
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(VMRGHH VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
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(VMRGHW VRRC:$vA, VRRC:$vA)>;
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// Immediate vector formation with vsplti*.
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def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
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