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Fix load-store optimizer on thumbv4t

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Thumbv4t does not have lo->lo copies other than MOVS,
and that can't be predicated. So emit MOVS when needed
and bail if there's a predicate.

http://reviews.llvm.org/D6592


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jonathan Roelofs
2015-01-21 22:39:43 +00:00
parent 448c4942e7
commit cab5680f6c
2 changed files with 69 additions and 3 deletions
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lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+14 -3
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@@ -567,10 +567,21 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
// MOV NewBase, Base
// ADDS NewBase, #imm8.
if (Base != NewBase && Offset >= 8) {
const ARMSubtarget &Subtarget = MBB.getParent()->getTarget()
.getSubtarget<ARMSubtarget>();
// Need to insert a MOV to the new base first.
BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);
if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&
!Subtarget.hasV6Ops()) {
// thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr
if (Pred != ARMCC::AL)
return false;
BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVSr), NewBase)
.addReg(Base, getKillRegState(BaseKill));
} else
BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);
// Set up BaseKill and Base correctly to insert the ADDS/SUBS below.
Base = NewBase;
BaseKill = false;