From cad1711154c7e6a1fba0e8cd75872c4ee6956fbf Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Thu, 14 Aug 2014 12:13:59 +0000 Subject: [PATCH] [x86] Begin stubbing out the AVX support in the new vector shuffle lowering scheme. Currently, this just directly bails to the fallback path of splitting the 256-bit vector into two 128-bit vectors, operating there, and then joining the results back together. While the results are far from perfect, they are *shockingly* good for what we're doing here. I'll be layering the rest of the functionality on top of this piece by piece and updating tests as I go. Note that 256-bit vectors in this mode are still somewhat WIP. While I think the code paths that I'm adding here are clean and good-to-go, there are still a lot of 128-bit assumptions that I'll need to stomp out as I march through the functional spread here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215637 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 88 ++++++++ test/CodeGen/X86/vector-shuffle-256-v4.ll | 258 ++++++++++++++++++++++ 2 files changed, 346 insertions(+) create mode 100644 test/CodeGen/X86/vector-shuffle-256-v4.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3f770200bb9..89c70497e5d 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8334,6 +8334,91 @@ static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2, } } +/// \brief Generic routine to split a 256-bit vector shuffle into 128-bit +/// shuffles. +/// +/// There is a severely limited set of shuffles available in AVX1 for 256-bit +/// vectors resulting in routinely needing to split the shuffle into two 128-bit +/// shuffles. This can be done generically for any 256-bit vector shuffle and so +/// we encode the logic here for specific shuffle lowering routines to bail to +/// when they exhaust the features avaible to more directly handle the shuffle. +static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1, + SDValue V2, + const X86Subtarget *Subtarget, + SelectionDAG &DAG) { + SDLoc DL(Op); + MVT VT = Op.getSimpleValueType(); + assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!"); + assert(V1.getSimpleValueType() == VT && "Bad operand type!"); + assert(V2.getSimpleValueType() == VT && "Bad operand type!"); + ShuffleVectorSDNode *SVOp = cast(Op); + ArrayRef Mask = SVOp->getMask(); + + ArrayRef LoMask = Mask.slice(0, Mask.size()/2); + ArrayRef HiMask = Mask.slice(Mask.size()/2); + + int NumElements = VT.getVectorNumElements(); + int SplitNumElements = NumElements / 2; + MVT ScalarVT = VT.getScalarType(); + MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2); + + SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1, + DAG.getIntPtrConstant(0)); + SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1, + DAG.getIntPtrConstant(SplitNumElements)); + SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2, + DAG.getIntPtrConstant(0)); + SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2, + DAG.getIntPtrConstant(SplitNumElements)); + + // Now create two 4-way blends of these half-width vectors. + auto HalfBlend = [&](ArrayRef HalfMask) { + SmallVector V1BlendMask, V2BlendMask, BlendMask; + for (int i = 0; i < SplitNumElements; ++i) { + int M = HalfMask[i]; + if (M >= NumElements) { + V2BlendMask.push_back(M - NumElements); + V1BlendMask.push_back(-1); + BlendMask.push_back(SplitNumElements + i); + } else if (M >= 0) { + V2BlendMask.push_back(-1); + V1BlendMask.push_back(M); + BlendMask.push_back(i); + } else { + V2BlendMask.push_back(-1); + V1BlendMask.push_back(-1); + BlendMask.push_back(-1); + } + } + SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask); + SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask); + return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask); + }; + SDValue Lo = HalfBlend(LoMask); + SDValue Hi = HalfBlend(HiMask); + return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); +} + +/// \brief High-level routine to lower various 256-bit x86 vector shuffles. +/// +/// This routine either breaks down the specific type of a 256-bit x86 vector +/// shuffle or splits it into two 128-bit shuffles and fuses the results back +/// together based on the available instructions. +static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2, + MVT VT, const X86Subtarget *Subtarget, + SelectionDAG &DAG) { + // FIXME: We should detect symmetric patterns and re-use the 128-bit shuffle + // lowering logic with wider types in that case. + + // FIXME: We should detect when we can use AVX2 cross-half shuffles to either + // implement the shuffle completely, more effectively build symmetry, or + // minimize half-blends. + + // Fall back to the basic pattern of extracting the high half and forming + // a 4-way blend. + return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG); +} + /// \brief Tiny helper function to test whether a shuffle mask could be /// simplified by widening the elements being shuffled. static bool canWidenShuffleElements(ArrayRef Mask) { @@ -8437,6 +8522,9 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget, if (VT.getSizeInBits() == 128) return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG); + if (VT.getSizeInBits() == 256) + return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG); + llvm_unreachable("Unimplemented!"); } diff --git a/test/CodeGen/X86/vector-shuffle-256-v4.ll b/test/CodeGen/X86/vector-shuffle-256-v4.ll new file mode 100644 index 00000000000..d26e1fbb0cb --- /dev/null +++ b/test/CodeGen/X86/vector-shuffle-256-v4.ll @@ -0,0 +1,258 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=AVX1 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-unknown" + +define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0001 +; AVX1: # BB#0: +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[0,1,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_0020(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0020 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm0[0] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_0112(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0112 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1],xmm1[0] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_0300(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0300 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[0],xmm1[1] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_1000(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_1000 +; AVX1: # BB#0: +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[2,3,0,1] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_2200(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_2200 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_3330(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_3330 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0] +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,2,3] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x i64> @shuffle_v4i64_3210(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_3210 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[2,3,0,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} + +define <4 x double> @shuffle_v4f64_0001(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_0001 +; AVX1: # BB#0: +; AVX1-NEXT: vmovlhps {{.*}} # xmm1 = xmm0[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_0020(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_0020 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm0[0] +; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_0300(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_0300 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[0],xmm1[1] +; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_1000(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_1000 +; AVX1: # BB#0: +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1,0] +; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_2200(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_2200 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vmovlhps {{.*}} # xmm1 = xmm1[0,0] +; AVX1-NEXT: vmovlhps {{.*}} # xmm0 = xmm0[0,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_3330(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_3330 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0] +; AVX1-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} +define <4 x double> @shuffle_v4f64_3210(<4 x double> %a, <4 x double> %b) { +; AVX1-LABEL: @shuffle_v4f64_3210 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[1,0] +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[1,0] +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> + ret <4 x double> %shuffle +} + +define <4 x i64> @shuffle_v4i64_0124(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0124 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm2[0],xmm1[1] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_0142(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0142 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm2[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[0],xmm2[1] +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_0412(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0412 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0] +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[0],xmm1[1] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_4012(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_4012 +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[0],xmm0[1] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_0145(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0145 +; AVX1: # BB#0: +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_0451(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_0451 +; AVX1: # BB#0: +; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm1[2,3,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm2[0],xmm0[1] +; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[0],xmm1[1] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_4501(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_4501 +; AVX1: # BB#0: +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +} +define <4 x i64> @shuffle_v4i64_4015(<4 x i64> %a, <4 x i64> %b) { +; AVX1-LABEL: @shuffle_v4i64_4015 +; AVX1: # BB#0: +; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm0[2,3,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm2[0],xmm1[1] +; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1] +; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[0],xmm0[1] +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq + %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> + ret <4 x i64> %shuffle +}