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always lower to RETFLAG, never leave it as just ret.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34639 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2007-02-26 19:44:02 +00:00
parent 5295692061
commit caddd44be7
2 changed files with 7 additions and 11 deletions
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15
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1626,13 +1626,13 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
} }
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy; SDOperand Chain = Op.getOperand(0);
switch(Op.getNumOperands()) { switch(Op.getNumOperands()) {
default: default:
assert(0 && "Do not know how to return this many arguments!"); assert(0 && "Do not know how to return this many arguments!");
abort(); abort();
case 1: case 1:
return SDOperand(); // ret void is legal return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
case 3: { case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg; unsigned ArgReg;
@ -1647,8 +1647,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
ArgReg = PPC::F1; ArgReg = PPC::F1;
} }
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), Chain = DAG.getCopyToReg(Chain, ArgReg, Op.getOperand(1), SDOperand());
SDOperand());
// If we haven't noted the R3/F1 are live out, do so now. // If we haven't noted the R3/F1 are live out, do so now.
if (DAG.getMachineFunction().liveout_empty()) if (DAG.getMachineFunction().liveout_empty())
@ -1656,9 +1655,9 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
break; break;
} }
case 5: case 5:
Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), Chain = DAG.getCopyToReg(Chain, PPC::R3, Op.getOperand(3), SDOperand());
SDOperand()); Chain = DAG.getCopyToReg(Chain, PPC::R4, Op.getOperand(1),
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); Chain.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now. // If we haven't noted the R3+R4 are live out, do so now.
if (DAG.getMachineFunction().liveout_empty()) { if (DAG.getMachineFunction().liveout_empty()) {
DAG.getMachineFunction().addLiveOut(PPC::R3); DAG.getMachineFunction().addLiveOut(PPC::R3);
@ -1666,7 +1665,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
} }
break; break;
} }
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Chain.getValue(1));
} }
static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,

3
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1080,9 +1080,6 @@ def : Pat<(xor GPRC:$in, imm:$imm),
def : Pat<(sub immSExt16:$imm, GPRC:$in), def : Pat<(sub immSExt16:$imm, GPRC:$in),
(SUBFIC GPRC:$in, imm:$imm)>; (SUBFIC GPRC:$in, imm:$imm)>;
// Return void support.
def : Pat<(ret), (BLR)>;
// SHL/SRL // SHL/SRL
def : Pat<(shl GPRC:$in, (i32 imm:$imm)), def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
(RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;